Hierarchical multi-threading processor

A method of executing instructions in a hierarchical microprocessor, the method comprising:

• obtaining the instructions for execution using a plurality of first-level instructions pipeline elements;
• storing first operand status information in the plurality of first-level instruction pipeline elements;
• dispatching, based on the first operand status information, the instructions to a plurality of second-level instruction pipeline elements included in respective execution clusters of the microprocessor;
• storing second operand status information for the instructions in the plurality of second-level instruction pipeline elements;
• dispatching, based on the second operand status information, the instructions to a plurality of respective execution units included in the execution clusters;
• and
• executing, in the respective execution units, one or more of the instructions,
• wherein the instructions include multiple execution threads.

A hierarchical microprocessor comprising:

• a plurality of first-level instruction pipeline elements;
• a plurality of execution clusters, each execution cluster being operatively coupled with each of the first-level instruction pipeline elements and including:
• a plurality of second-level instruction pipeline elements, wherein each of the second-level instruction pipeline elements corresponds with a respective first-level instruction pipeline element;
• and
• one or more instruction execution units operatively coupled with each of the second-level instruction pipeline elements,
• wherein:
• the microprocessor is configured to execute multiple execution threads using the plurality of first-level instruction pipeline elements, the plurality of second-level instruction pipeline elements and the plurality of execution clusters;
• and
• the first-level instruction pipeline elements and the second-level instruction pipeline elements each include:
• an instruction scheduler;
• a store buffer;
• and
• a register file structure.

A method of executing instructions in a hierarchical microprocessor, the method comprising:

• obtaining the instructions for execution using a plurality of first-level instructions pipeline elements;
• storing first operand status information in the plurality of first-level instruction pipeline elements;
• dynamically assigning the execution threads to respective execution clusters;
• dispatching, based on the first operand status information the dynamic assignment, the instructions to a plurality of second-level instruction pipeline elements included in respective execution clusters of the microprocessor;
• storing second operand status information for the instructions in the plurality of second-level instruction pipeline elements;
• dispatching, based on the second operand status information, the instructions to a plurality of respective execution units included in the execution clusters;
• executing, in the respective execution units, one or more of the instructions,
• wherein the instructions include multiple execution threads, and
• moving execution of at least one execution thread from a first execution cluster to a second execution cluster.