Test control circuit
AssigneeNEC Electronics Corporation
InventorKousaku HARADA
Life of this patent
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Abstract
In a conventional semiconductor device, to effectively improve a toggling coefficient of a memory circuit, a test pattern and the like must be inputted from the outside, and there has been a problem that it is difficult to improve the toggling coefficient in a dynamic BT unless a high capability device is used. A test control circuit 4 according to the present invention detects the termination of a memory test executed by a BIST circuit 2A, and comprises a detector 12 for outputting a reset signal and a BIST circuit controller 13 for allowing the BIST circuit 2A to be repeatedly operated based on the reset signal.
Claims17
A test control circuit comprising:
- a detector associated with a BIST circuit to generate a reset signal indicative of a termination of a macro test executed by said BIST circuit;
- and
- a controller allowing said BIST circuit to repeatedly operate in response to said reset signal.
A test control method of a semiconductor device comprising a macro and a BIST circuit for executing a test of the macro, wherein said method comprising:
- generating a reset signal indicative of a termination of the macro test executed by said BIST circuit;
- and
- allowing said BIST circuit to repeatedly operate in response to said reset signal.
Dependencies are inferred from the claim text.