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US 2008/0076246 A1Published application
Through contact layer opening silicide and barrier layer formation
OwnerBrennan L. Peterson, Vinay B. Chikarmane +1inventors
InventorsBrennan L. Peterson, Vinay B. Chikarmane, Kevin J. Fischer
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Abstract
Embodiments of the invention include apparatuses and methods relating to through contact-opening silicide and barrier layer formation. In one embodiment, a silicide region is formed in a silicon substrate by deposition of a siliciding material in a contact opening and a subsequent anneal.
Claims23
A method of forming a silicide region for a transistor contact comprising:
- forming a dielectric layer having an opening over a substrate including silicon;
- depositing a siliciding material over the dielectric layer and the substrate within the opening such that a doped region is formed in the substrate within the opening, wherein the doped region has atoms of the siliciding material included in the substrate;
- and
- annealing the doped region to form the silicide region.
1 more element
A method comprising:
- forming a dielectric layer having an opening over a substrate including silicon;
- depositing by physical vapor deposition at a first bias voltage a siliciding material over the dielectric layer and the substrate within the opening such that a doped region is formed in the substrate within the opening, wherein the doped region has atoms of the siliciding material included in the substrate;
- depositing by physical vapor deposition at a second bias voltage a barrier layer over the siliciding material, wherein the first bias voltage is greater than the second bias voltage;
- and
- annealing the doped region to form a silicide region in the substrate.
2 more elements
A method comprising:
- forming a dielectric layer having an opening over a transistor, the transistor including a source region and a drain region separated by a channel region, and a gate structure including a gate dielectric and a gate electrode over the channel region, wherein the opening is over a portion of the source region;
- depositing by physical vapor deposition at a first bias voltage a siliciding material over the dielectric layer and the source region within the opening such that a doped region is formed in the source region within the opening, wherein the doped region has atoms of the siliciding material included in the substrate;
- depositing by physical vapor deposition at a second bias voltage a barrier layer over the siliciding material, wherein the first bias voltage is greater than the second bias voltage;
- and
- annealing the doped region to form a silicide in a first area of the source region, wherein the source region includes a second area that does not include the silicide.
2 more elements
A transistor comprising:
- a source region and a drain region in a substrate, wherein the source region and the drain region are separated by a channel region;
- a gate structure including a gate dielectric and a gate electrode over the channel region;
- a silicide region formed within a first area of a surface of the source region, wherein the surface of the source region includes a second area that includes a bulk doped source region material that is in contact with a contact layer dielectric material, and wherein the silicide region comprises at least one of tantalum, titanium, nickel, cobalt, or molybdenum.
Dependencies are inferred from the claim text.