Nonvolatile semiconductor memory and a fabrication method for the same

A fabrication method for a nonvolatile semiconductor memory comprising:

• forming a polysilicon layer for floating gates, and then forming an etching trench for device isolating region formation by selectively removing the polysilicon layer for the floating gates;
• forming a device isolating region by depositing an insulator film across the entire surface of the device for filling in that etching trench, and then planarizing until exposing the polysilicon layer for the floating gates;
• successively depositing an inter-gate insulating film, a control gate, and a mask insulator film across the entire planarized surface;
• successively removing select gate transistors in an area other than a memory cell transistor area, the mask insulator in a peripheral transistor area, the control gate, and the inter-gate insulator film, and then etching the filling material of the device isolating region such that the surface of the device isolating region is at a lower position than the bottom of the inter-gate insulator film;
• depositing a conductive material for sidewall gates, and then etching until exposing the surface of the mask insulator film, and stopping the etching process at the top of the floating gates so as to form sidewall gates;
• and
• forming isolated memory cell transistor areas and select gate transistor areas.

A fabrication method for a nonvolatile semiconductor memory including a memory cell transistor and a select gate transistor, comprising:

• successively forming a first gate insulator film, a first conductor layer, a second gate insulator film, a second conductor layer and a mask film on a semiconductor substrate;
• successively removing the mask film, the second conductor layer and the second gate insulator film so as to expose an upper surface of the first conductor layer and a side surface of the second conductor layer, in a first region where a side gate electrode of the select gate transistor is formed;
• forming a third conductor layer on the upper surface of the first conductor layer and the side surface of the second conductor layer;
• and
• removing the mask film, the second gate insulator film and the first conductor film in a second region except the first region, while leaving the third conductor layer, so as to form a first gate electrode of the memory cell transistor including a floating gate and a control gate and a second gate electrode of the select gate transistor including a first portion where the second insulator film is located between the first and the second conductor layers and a second portion where the side gate electrode is located between the first and the second conductor layers.