Methods of Reducing Coupling Between Floating Gates in Nonvolatile Memory
AssigneeSanDisk Corporation
InventorsHenry Chien, George Matamis, Tuan Pham, Masaaki Higashitani, Hidetaka Horiuchi, Jeffrey W. Lutze, Nima Mokhlesi, Yupin Kawing Fong
Life of this patent
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Abstract
A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
Claims19
A method of forming an array of non-volatile memory cells on a semiconductor substrate surface, comprising:
- forming a plurality of shallow trench isolation structures that extend in a first direction;
- forming a plurality of first conductive portions that extend in the first direction;
- forming a slot over an individual one of the first conductive portions, the slot being narrower than the first conductive portion in a second direction that is perpendicular to the first direction;
- forming a second conductive portion in the slot, the second conductive portion in electrical contact with the first conductive portion;
- and
- forming a plurality of floating gates by etching the first and second conductive portions.
A method of forming an array of non-volatile memory cells on a semiconductor substrate having a surface, comprising:
- forming a plurality of shallow trench isolation structures that extend in a first direction and are spaced apart in a second direction that is perpendicular to the first direction, the plurality of shallow trench isolation structures separated by a plurality of first conductive portions;
- subsequently forming a plurality of sidewall spacers that extend in the first direction along exposed sidewalls of ones of the plurality of shallow trench isolation structures, the plurality of sidewall spacers overlying first conductive portions;
- subsequently forming a plurality of second conductive portions defined by the plurality of sidewall spacers and contacting the first conductive portions;
- and
- subsequently removing the plurality of sidewall spacers thereby exposing surfaces of the plurality of first conductive portions and the plurality of second conductive portions.
A method of forming a memory array, comprising:
- forming a conductive floating gate layer;
- forming a plurality of masking portions over the floating gate layer, the plurality of masking portions extending in a first direction and separated in a second direction;
- subsequently performing a first etch to remove portions of the floating gate layer that are exposed by the plurality of masking portions, the removed portions extending to a depth that is less than the thickness of the floating gate layer;
- subsequently forming a plurality of sidewall spacers that extend in the first direction on exposed surfaces of the floating gate layer;
- and
- subsequently performing a second etch to form a plurality of trenches in the substrate, an individual one of the plurality of trenches extending in the first direction and having an extent in the second direction defined by ones of the plurality of sidewall spacers.
Dependencies are inferred from the claim text.