Method to fabricate high-k/metal gate transistors using a double capping layer process
OwnerSangwoo Pae, Jose Maiz +1inventors
InventorsSangwoo Pae, Jose Maiz, Chetan Prasad
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Abstract
Semiconductor devices and methods to fabricate thereof are described. For an embodiment, a semiconductor device features a double capping layer. The double capping layer may include a first-capping layer and a second-capping layer. The first-capping layer protects a high-k gate dielectric film during a replacement gate process and the second-capping layer protects the first-capping layer during metal deposition. For other embodiments, the first-capping layer prevents the interaction between a polysilicon layer and a high-k gate dielectric film to prevent Vt-pinning of fabricated transistors.
Claims22
A device, comprising:
- a substrate;
- an interlayer dielectric disposed on a top surface of said substrate, wherein said interlayer dielectric comprises a first portion and a second portion;
- a gate dielectric layer disposed between said first and second portions of said interlayer dielectric and over said substrate;
- a first-capping layer disposed between said first and second portions of said interlayer dielectric and on said gate dielectric layer;
- a second-capping layer disposed between said first and second portions of said interlayer dielectric and on said first-capping layer;
- and
- a metal gate electrode disposed between said first and second portions of interlayer dielectric and on said second-capping layer;
A semiconductor device, comprising:
- a semiconductor substrate;
- an interlayer dielectric disposed on a top surface of said substrate, wherein said interlayer dielectric comprises a first portion and a second portion;
- a high-k gate dielectric layer disposed between said first and second portions of said interlayer dielectric and over said substrate;
- a first-capping layer disposed between said first and second portions of interlayer dielectric and on said high-k gate dielectric layer;
- an atomic deposition layer disposed between said first and second portions of said interlayer dielectric and on said first-capping layer;
- a metal gate electrode disposed between said first and second portions of said interlayer dielectric and over said atomic deposition layer;
- a source and drain region disposed within said substrate and adjacent to said interlayer dielectric and said set of spacers;
- a channel region disposed within said substrate and adjacent to said high-k gate dielectric layer and said source and drain regions;
- and
- a set of spacers adjacent to said high-k gate dielectric layer, first-capping layer, second-capping layer, and said metal gate electrode.
A method, comprising
- depositing a high-k gate dielectric layer on a semiconductor substrate,
- depositing a first-capping layer on said high-k gate dielectric layer;
- forming a sacrificial gate electrode material on said first-capping layer;
- etching said high-k gate dielectric layer, first-capping layer, and said sacrificial gate electrode material to define a sacrificial gate stack;
- depositing a set of spacers adjacent to said sacrificial gate stack;
- implanting dopants in said semiconductor substrate to define a source and drain region;
- depositing an interlayer dielectric on said semiconductor substrate and adjacent to said set of spacers;
- etching said sacrificial gate electrode material to expose said first-capping layer and to define a trench;
- and
- forming a second-capping layer within said trench and on said first-capping layer by an atomic layer deposition process.
- filling said trench with a metal gate material to form a metal gate electrode.
Dependencies are inferred from the claim text.