Method of forming a fine pattern

A method of forming a fine pattern, the method comprising:

• forming a first layer and a second layer on a semiconductor substrate;
• forming a third layer on the second layer having a thickness smaller than those of the first and the second layers;
• forming a first mask pattern having a first space on the third layer, wherein the first space is configured to partially expose the third layer;
• forming a third layer pattern having a second space configured to partially expose the second layer by removing a portion of the third layer exposed by the first space;
• forming a first sacrificial layer on a top surface of the first mask pattern, a sidewall and a bottom of the second space, and the second layer;
• forming a fourth layer on the first sacrificial layer, wherein the fourth layer is configured to form a second mask pattern having an etching ratio substantially the same as that of the first mask pattern;
• forming a double mask pattern including the first mask pattern and the second mask pattern by partially removing the fourth layer to form the second mask pattern filled in the second space;
• forming a preliminary second sacrificial layer on the first sacrificial layer;
• forming a second sacrificial layer by removing the preliminary second sacrificial layer until the top surface of the double mask pattern is exposed;
• forming a sacrificial layer pattern having a third space by performing an etching process using an etching selectivity between the second sacrificial layer and the double mask pattern to remove the double mask pattern, the third layer pattern, and a first portion of the first sacrificial layer disposed beneath the second mask pattern, wherein the third space partially exposes the second layer, and the sacrificial layer pattern includes a second portion of the first sacrificial layer and the second sacrificial layer;
• forming a preliminary insulation layer pattern having a fourth space by performing an etching process using an etching selectivity between the second layer and the sacrificial layer pattern to remove a third portion of the second layer exposed by the third space, wherein the fourth space partially exposes the first layer;
• and
• forming an insulation layer pattern having a fifth space by performing an etching process using an etching selectivity between the preliminary insulation layer pattern and the first layer to remove a fourth portion of the first layer exposed by the fourth space, wherein the fifth space partially exposes the semiconductor substrate.