Graphics Processors With Parallel Scheduling and Execution of Threads

An integrated circuit comprising:

• a plurality of hardware units operable in parallel, each hardware unit supporting a respective set of operations;
• and
• a scheduler operable to dispatch instructions for multiple threads to the plurality of hardware units concurrently.

A graphics processor comprising:

• an instruction random access memory (RAM) operative to store instructions for at least one graphics program;
• and
• a tag RAM operative to store tags and hardware identifiers for the instructions stored in the instruction RAM, the hardware identifiers indicating hardware units to use for the instructions.

An integrated circuit comprising:

• an instruction random access memory (RAM) operative to store instructions for at least one graphics program;
• and
• a tag RAM operative to store tags and hardware identifiers for the instructions stored in the instruction RAM, the hardware identifiers indicating hardware units to use for the instructions.

A graphics processor comprising:

• a plurality of register banks operative to store graphics data;
• and
• an arbitration unit operative to receive from a plurality of hardware units requests to access the plurality of register banks, to perform arbitration for the requests, and to couple the plurality of register banks to hardware units granted access.

An integrated circuit comprising:

• a plurality of register banks operative to store graphics data;
• and
• an arbitration unit operative to receive from a plurality of hardware units requests to access the plurality of register banks, to perform arbitration for the requests, and to couple the plurality of register banks to hardware units granted access.

A wireless device comprising:

• a graphics processor operative to perform graphics operations and comprising
• a plurality of hardware units operable in parallel, each hardware unit supporting a respective set of operations, and
• a scheduler operable to dispatch instructions for multiple threads to the plurality of hardware units concurrently.