Delta-sigma AD converter

A Delta-Sigma AD converter comprising:

• a subtractor outputting a difference of two analog input signals;
• a first integrator integrating the output of the subtracter;
• a quantizer quantizing the output signal of the first integrator;
• a digital-to-analog converter outputting an analog signal in proportion to the output signal of the quantizer;
• a first switching circuit that, for each predetermined sampling timing, switches the output signal of the digital-to-analog converter and successively outputs the output signal to different output paths;
• a first feedback circuit having a plurality of charge-holding circuits respectively connected to different output paths from the first switching circuit, with the charge-holding circuits holding respectively differing amounts of feedback of a signal in proportion to the magnitude of the output signal of the digital-to-analog converter during predetermined sampling time intervals;
• a second switching circuit that, for each sampling timing, switches the signal held in the first feedback circuit and outputs the signal to one of the input terminals of the subtracter,
• an input portion that, for each predetermined sampling timing, holds a signal in proportion to the analog input signal during a fixed sampling time interval;
• a third switching circuit that, for each predetermined sampling timing, switches the output signal of the first integrator and successively outputs the output signal to different output paths;
• a second feedback circuit having a plurality of charge-holding circuits respectively connected to different output paths from the third switching circuit, with the charge-holding circuits holding differing amounts of feedback of a signal in proportion to the magnitude of the output signal of the first integrator input from the third switching circuit during predetermined sampling time intervals;
• and
• a fourth switching circuit that, for each sampling timing, switches a signal held in the input portion and a signal held in the second feedback circuit and inputs the signal to the other input terminal of the subtractor;
• wherein the plurality of signals of different sampling timings held in the first and second feedback circuits are integrated accumulatively in the subtracter and first integrator.