US 2008/0074162 A1 · DATA LATCH CIRCUIT WITH A PHASE SELECTOR

Abstract

The present invention provides a data latch circuit. The data latch circuit includes a first data latch unit, a second data latch unit, a third data latch unit, and a phase selector. The first data latch unit is used for latching a first input data according to a first clock signal and outputting a first output data. The second data latch unit is used for latching the first output data according to a second clock signal and outputting a second output data. The third data latch unit is used for latching the second output data according to a third clock signal and outputting an output data. The phase selector is coupled to the second data latch unit for generating the second clock signal to the second data latch unit according to phase relation between the first clock signal and the third clock signal.

Claims18

Dependent claims

A data latch circuit comprising:

a first data latch unit, for latching a first input data according to a first clock signal and outputting a first output data;
a second data latch unit, coupled to the first data latch unit, for latching the first output data according to a second clock signal and outputting a second output data;
a third data latch unit, coupled to the second data latch unit, for latching the second output data according to a third clock signal and outputting an output data;
and
a phase selector, coupled to the second data latch unit, for generating the second clock signal to the second data latch unit according to a phase relation between the first clock signal and the third clock signal.

2 more elements

Dependencies are inferred from the claim text.

Data latch circuit with a phase selector

Life of this patent

Data latch circuit with a phase selector

Life of this patent

Abstract

Claims18