Delay Circuit
AssigneeQimonda AG
InventorsPatrick Heyne, Per Johansson
Life of this patent
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Abstract
A delay circuit includes a delay device, to which an input signal is supplied. A first phase-shifted signal can be generated by the delay device, which is delayed by a first delay time with respect to the input signal, and a second phase-shifted signal can be generated, which is delayed by a second delay time with respect to the input signal. The delay device is configured such that the first and second phase-shifted signal can be generated in inverted fashion with respect to one another at an output terminal of the delay device after a delay of the input signal by a delay time.
Claims18
A delay circuit, comprising:
- a controllable delay device configured to generate first and second signals that are phase-shifted with respect to an input signal of the delay device;
- a feedback circuit configured to generate a feedback signal that is phase-shifted with respect to one of the first or second phase-shifted signals selectively supplied to the feedback circuit;
- a first phase comparison device configured to perform a phase comparison of the input signal of the delay device and the feedback signal;
- and
- a control circuit configured to set first and second delay times by which the controllable delay device respectively delays the first and second phase-shifted signals, the first and second delay times depending on the phase comparison performed by the first phase comparison device;
- wherein the controllable delay device is configured to generate the first and second phase-shifted signals in inverted fashion with respect to one another at respective first and second output terminals of the controllable delay device after a delay of the input signal by a delay time.
A method of operating a delay circuit, the method comprising:
- applying an input signal with a first frequency to an input terminal of a controllable delay device of the delay circuit;
- generating a first signal that is phase-shifted with respect to the input signal by delaying the input signal in the controllable delay device by a first delay time;
- and
- generating a second signal that is phase-shifted with respect to the input signal by delaying the input signal in the controllable delay device by a second delay time, wherein a level of the first phase-shifted signal generated via the controllable delay device is outputted in inverted fashion with respect to a level of the second phase-shifted signal;
- generating a feedback signal via a feedback circuit in response to receiving the first phase-shifted signal, wherein the feedback signal is delayed by a further delay time with respect to the first phase-shifted signal;
- comparing a phase of the input signal with a phase of the feedback signal;
- varying the first delay time until a phase difference between the feedback signal and the first phase-shifted signal corresponds to an integral multiple of a period duration of the input signal or until the first phase-shifted signal is delayed by a delay time with respect to the input signal;
- generating the feedback signal via the feedback circuit in response to receiving the second phase-shifted signal;
- comparing a phase of the input signal with a phase of the feedback signal;
- varying the second delay time until a phase difference between the feedback signal and the second phase-shifted signal corresponds to an integral multiple of a period duration of the input signal or until the second phase-shifted signal is delayed by a delay time with respect to the input signal;
- and
- selectively feeding the first or second phase-shifted signal to an output terminal of the delay circuit, wherein the first phase-shifted signal is supplied to the output terminal if the first delay time is less than the second delay time and the second phase-shifted signal is supplied to the output terminal of the delay circuit if the second delay time is less than the first delay time.
Dependencies are inferred from the claim text.