Dual-edge-triggered, clock-gated logic circuit and method
AssigneeSamsung Electronics Co., Ltd.
InventorMin-Su KIM
Life of this patent
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Abstract
A dual-edge-triggered clock-gated logic circuit includes; a delay clock generator operating to generate first, second, third and fourth delay clock signals in response to a clock signal, and a pulse generator operating to generate a pulse signal in response to the clock signal, the first, third, and fourth delay clock signals, and the control signal. The pulse generator operates to generate the pulse signal at the rising and falling edges of the clock signal.
Claims19
A dual-edge-triggered clock-gated logic circuit comprising:
- a delay clock generator operating to generate first, second, third and fourth delay clock signals in response to a clock signal;
- and
- a pulse generator operating to generate a pulse signal in response to the clock signal, the first, the third, and the fourth delay clock signals, and the control signal,
- wherein the pulse generator operates to generate the pulse signal at the rising and falling edges of the clock signal.
A low power logic circuit comprising:
- a dual-edge-triggered clock-gated logic circuit generating a pulse signal at the rising and falling edges of a clock signal;
- and
- a logic circuit operating synchronously with the pulse signal,
- wherein the logic circuit includes a plurality of latches driven by the pulse signal.
A method for operating a dual-edge-triggered clock-gated logic circuit, comprising:
- generating a first delay clock signal by inverting and delaying a clock signal by a first delay period;
- generating a second delay clock signal by inverting and delaying the first delay clock signal by a second delay period;
- generating a third delay clock signal by inverting and delaying the second delay clock signal;
- generating a fourth delay clock signal by inverting and delaying the third delay clock signal;
- and
- generating a pulse signal in response to the clock signal, the first, third, and fourth delay clock signals, and a control signal,
- wherein the pulse signal is generated at the rising and falling edges of the clock signal during an active period defined by the control signal.
Dependencies are inferred from the claim text.