High speed level shifter
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsAnkit Srivastava, Sourav Jandial
Life of this patent
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Abstract
Embodiments of the present invention provide level shifter circuits capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS devices, when the input signal switches from a high logic level to a low logic level. The dynamic charge injection device is incorporated at output nodes to provide initial thrust to the level shifter circuits, which triggers a positive regenerative feedback of cross-coupled pull up PMOS devices enabling a rapid transition and hence the high frequency operation.
Claims22
1-4. (canceled)
A method of shifting a voltage level by diminishing a capacitive coupling effect in a high speed level shifter circuit for a high frequency operation comprising the following steps:
- switching of a first input signal alternately from a high logic level to a low logic level and a low logic level to a high logic level;
- switching of a second input signal alternately from the low logic level to the high logic level and the high logic level to the low logic level;
- turning on a dynamic charge injection device to inject current into an output node to nullify a capacitive coupling effect between an input node and the output node;
- charging of the output node to initiate triggering of a regenerative feedback among cross coupled PMOS devices to get a voltage level shift with a high speed.
A level shifter circuit comprising MOS input devices and cross-coupled MOS pull-up devices, each MOS pull-up device being coupled in series with a respective one of the MOS input devices, and each of the MOS input devices including an input node adapted to receive an input signal and including a signal node coupled to a corresponding output node of the level shifter circuit, the level shifter circuit further comprising a dynamic charge injection device coupled to each output node, each dynamic charge injection device operable responsive to the input signal applied to a corresponding one of the MOS input devices to reduce a capacitive coupling between the input node and the corresponding output node.
An integrated circuit, comprising:
- core electronic circuitry operable at a low supply voltage;
- and
- a level shifter circuit coupled to the core electronic circuitry and toe input/output pads, the level shifter circuit comprising MOS input devices and cross-coupled MOS pull-up devices, each MOS pull-up device being coupled in series with a respective one of the MOS input devices, and each of the MOS input devices including an input node adapted to receive an input signal and including a signal node coupled to a corresponding output node of the level shifter circuit, the level shifter circuit further comprising a dynamic charge injection device coupled to each output node, each dynamic charge injection device operable responsive to the input signal applied to a corresponding one of the MOS input devices to reduce a capacitive coupling between the input node and the corresponding output node.
An electronic system, comprising:
- electronic components including an integrated circuit, the integrated circuit comprising,
- core electronic circuitry operable at a low supply voltage;
- and
- a level shifter circuit coupled to the core electronic circuitry and toe input/output pads, the level shifter circuit comprising MOS input devices and cross-coupled MOS pull-up devices, each MOS pull-up device being coupled in series with a respective one of the MOS input devices, and each of the MOS input devices including an input node adapted to receive an input signal and including a signal node coupled to a corresponding output node of the level shifter circuit, the level shifter circuit further comprising a dynamic charge injection device coupled to each output node, each dynamic charge injection device operable responsive to the input signal applied to a corresponding one of the MOS input devices to reduce a capacitive coupling between the input node and the corresponding output node.
A method of controlling a level shifting circuit including first and second NMOS transistors and first and second cross-coupled PMOS transistors, the first and second NMOS transistors adapted to receive first and second input signals, respectively, and driving first and second output nodes, respectively, the method comprising:
- providing charge to one of the first and second output nodes responsive to the first input signal transitioning from a first logic state to a second logic state and the second input signal transitioning from the second logic state to the first logic state, and wherein the provided charge is not provided by the corresponding PMOS transistor;
- and
- providing charge to the other one of the first and second output nodes responsive to the second input signal transitioning from the first logic state to the second logic state and the first input signal transitioning from the second logic state to the first logic state, and wherein the charge is not provided by the corresponding PMOS transistor.
Dependencies are inferred from the claim text.