Semiconductor package

A semiconductor package comprising:

• upper and lower semiconductor packages sequentially stacked,
• wherein each of the upper and lower semiconductor packages comprises:
• a semiconductor chip;
• a plurality of inner leads comprising upper surfaces, side surfaces, and bottom surfaces, the plurality of inner leads electrically connected to the semiconductor chip;
• and
• an encapsulant covering the semiconductor chip and the inner leads,
• wherein portions of the bottom and side surfaces of the inner leads are exposed from the encapsulants, the bottom surfaces of the inner leads are disposed at a different height from bottom surfaces of the encapsulants, and the inner leads of the upper semiconductor package are electrically connected to the inner leads of the lower semiconductor package.

A method of manufacturing a stacked semiconductor package, the method comprising:

• forming a first package, wherein forming the first package comprises:
• connecting a plurality of first inner leads to a first semiconductor chip with a plurality of first bond wires;
• and
• encapsulating the first semiconductor chip, the first bond wires and a portion of the first inner leads with a first encapsulant, wherein the bottom surfaces of the first inner leads are recessed or protruded with respect to the bottom surface of the first encapsulant;
• forming a second package, wherein forming the second package comprises:
• connecting a plurality of second inner leads to a second semiconductor chip with a plurality of second bond wires;
• and
• encapsulating the second semiconductor chip, the second bond wires and a portion of the second inner leads with a second encapsulant, wherein the bottom surfaces of the second inner leads are recessed or protruded with respect to the bottom surface of the second encapsulant;
• stacking the second package on the first package;
• and
• electrically connecting the first inner leads to the second inner leads.

A semiconductor package comprising:

• a semiconductor chip;
• a plurality of inner leads comprising upper surfaces and bottom surfaces, the plurality of inner leads electrically connected to the semiconductor chip;
• and
• an encapsulant covering the semiconductor chip and the plurality of inner leads,
• wherein portions of the bottom surfaces of the inner leads are exposed from the encapsulant and the exposed portions of the bottom surfaces of the inner leads are not coplanar with a bottom surface of the encapsulant.