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US 2008/0073706 A1Published application
High withstand voltage trenched MOS transistor and manufacturing method thereof
AssigneeSharp Kabushiki Kaisha
InventorKeiji Hayashi
Life of this patent
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Abstract
A high withstand voltage transistor includes: a gate electrode provided in a trench formed on a semiconductor substrate; a source and a drain which are respectively formed on a side of the gate electrode and another side of the gate electrode, and which are a predetermined distance away from the gate electrode; first electric field relaxation layers one of which is formed on a wall of the trench on the side of the source and another one of which is formed on a wall of the trench on the side of the drain; and second electric field relaxation layers one of which is formed between the source and the gate electrode, and another one of which is formed between the drain and the gate electrode.
Claims20
A high withstand voltage trenched MOS transistor, comprising:
- a trench formed on a semiconductor substrate and a gate oxidized film formed in a surface portion of the trench;
- a gate electrode formed on the gate oxidized film in the trench;
- first electric field relaxation layers one of which is formed in a surface portion of the semiconductor substrate adjacent to one side of the gate electrode, and another one of which is formed in a surface portion of the semiconductor substrate adjacent to another side of the gate electrode;
- second electric field relaxation layers each of which is formed along a wall of the trench in a region having the gate electrode, and is connected to one of the first electric field relaxation layers;
- an insulation film covering the gate electrode;
- and
- a source region and a drain region one of which is formed so as to be included in a surface portion of one of the first electric field relaxation layers provided on the side of the gate electrode, and another one of which is formed so as to be included in a surface portion of another one of the first electric field relaxation layers provided on the other side of the gate electrode.
4 more elements
A high withstand voltage trenched MOS transistor, comprising:
- a trench formed on a semiconductor substrate and a gate oxidized film formed on walls of the trench;
- a gate electrode formed on the gate oxidized film in the trench and is extended to regions of the semiconductor substrate adjacent to the trench;
- a side wall formed on one side of the extended portion of the gate electrode on the semiconductor substrate, and another side wall formed on another side of the extended portion of the gate electrode;
- first electric field relaxation layers one of which is formed in a surface portion of the semiconductor substrate adjacent to one side of the gate electrode, and another one of which is formed in a surface portion of the semiconductor substrate adjacent to another side of the gate electrode;
- second electric field relaxation layers each of which is formed along one of the walls of the trench having the gate electrode, and is connected to one of the first electric field relaxation layers;
- and
- a source region and a drain region one of which is formed so as to be included in a surface portion of one of the first electric field relaxation layers provided on the side of the gate electrode, and another one of which is formed so as to be included in a surface portion of another one of the first electric field relaxation layers provided on the other side of the gate electrode.
4 more elements
A high withstand voltage trenched MOS transistor, comprising:
- a trench formed on a semiconductor substrate and a gate oxidized film formed on walls of the trench;
- a gate electrode formed on the gate oxidized film in the trench so that a top surface of the gate electrode is lower than surface portions of the semiconductor substrate adjacent to the trench;
- a side wall formed on the top surface of the gate electrode and is extended along one of the walls of the trench;
- first electric field relaxation layers one of which is formed in a surface portion of the semiconductor substrate adjacent to one side of the gate electrode, and another one of which is formed in a surface portion of the semiconductor substrate adjacent to another side of the gate electrode;
- second electric field relaxation layers each of which is formed along one of the walls of the trench having the gate electrode, and is connected to one of the first electric field relaxation layers;
- and
- a source region and a drain region one of which is formed so as to be included in a surface portion of one of the first electric field relaxation layers provided on the side of the gate electrode, and another one of which is formed so as to be included in a surface portion of another one of the first electric field relaxation layers provided on the other side of the gate electrode.
4 more elements
A method of manufacturing a high withstand voltage trenched MOS transistor, comprising the steps of:
- (I) forming a trench on a first conductive semiconductor substrate and burying a CVD oxidized film;
- (II) forming second electric field relaxation layers by implanting a second conductive ion along walls on two sides of the trench in a transistor formation region, using resist as a mask;
- (III) removing the CVD oxidized film from the trench in the transistor formation region, and forming a gate oxidized film on the walls and the bottom surface of the trench exposed on the semiconductor substrate;
- (IV) burying a gate electrode in the trench;
- (V) forming an insulation film having an intended width for covering the gate electrode;
- (VI) forming first electric field relaxation layers by implanting a second conductive ion, using the insulation film as a mask;
- and
- (VII) forming a source region and a drain region by implanting a second conductive ion, using the insulation film as a mask.
5 more elements
Dependencies are inferred from the claim text.