US 2008/0073698 A1 · Nonvolatile semiconductor memory element and nonvolatile semiconductor memory device

Abstract

The channel of each nonvolatile semiconductor memory element has a plate-like shape, and a charge accumulating layer is formed on one face of the channel region, with an insulating film being interposed in between. A control gate electrode is then formed on the charge accumulating layer, with another insulating film being interposed in between. Another control gate electrode is formed on the other face of the channel region, with yet another insulating film being interposed in between. The plate-like semiconductor region is designed to have a thickness smaller than twice the largest depletion layer thickness determined by the impurity concentration. In this manner, variations of the threshold voltages varying with the voltage of the control gate electrodes can be made smaller than the minimum value in conventional elements. As a result, nonvolatile semiconductor memory elements that have higher controllability over threshold voltages and can lower the power supply voltage so as to reduce the power consumption can be provided.

Claims24

Dependent claims

A nonvolatile semiconductor memory element comprising:

a semiconductor region of a first conductivity type having a plate-like shape, on a semiconductor substrate;
a first insulating film to cover a first face of the semiconductor region;
a charge accumulating layer to cover the first insulating film;
a second insulating film to cover the charge accumulating layer;
a first control gate electrode to cover the second insulating film;
a third insulating film to cover a second face of the semiconductor region, the second face being the opposite face to the first face;
a second control gate electrode to cover the third insulating film;
and
source/drain regions of a second conductivity type sandwiching the charge accumulating layer, in the semiconductor region, the source/drain regions and the charge accumulating layer having at least one overlapping portion,
wherein the semiconductor region has a thickness equal to or smaller than twice the largest depletion layer thickness determined by an impurity concentration in the semiconductor region, and the first control gate electrode and the second control gate electrode are electrically joined to each other.

7 more elements

A nonvolatile semiconductor memory element comprising:

a SOI substrate including a semiconductor supporting substrate, an embedded insulating film on the semiconductor supporting substrate, and a semiconductor layer of a first conductivity type on the embedded insulating film;
source/drain regions of a second conductivity type in the semiconductor layer at a distance from each other;
a first insulating film on a portion of the semiconductor layer, the portion being located between the source/drain regions;
a charge accumulating layer on the first insulating film;
a second insulating film on the charge accumulating layer;
a first control gate electrode on the second insulating film;
and
a second control gate electrode in a portion of the semiconductor supporting substrate located immediately below the embedded insulating film, the second control gate electrode being perpendicular to the first control gate electrode,
wherein:
the source/drain regions sandwich the charge accumulating layer and are formed in the semiconductor layer, the source/drain regions and the charge accumulating layer having at least one overlapping portion;
and
the semiconductor layer has a thickness equal to or smaller than twice the largest depletion layer thickness determined by an impurity concentration in the semiconductor layer.

9 more elements

Dependencies are inferred from the claim text.

Nonvolatile semiconductor memory element and nonvolatile semiconductor memory device

Life of this patent

Nonvolatile semiconductor memory element and nonvolatile semiconductor memory device

Life of this patent

Abstract

Claims24