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US 2008/0073689 A1Published application
Program/erase schemes for floating gate memory cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Tsong Wang, Tong-Chern Ong
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Abstract
A flash memory cell includes a substrate, a blocking layer over the substrate, a floating gate over the blocking layer, a retention layer over the floating gate, a control gate over the retention layer, a tunneling layer over the control gate, a top gate over the tunneling layer, and a voltage source electrically coupled between the top gate and the control gate. Various charge tunneling mechanisms may be used for charges to tunnel through the retention layer.
Claims20
A semiconductor device comprising:
- a substrate;
- a blocking layer over the substrate;
- a floating gate over the blocking layer;
- a retention layer over the floating gate;
- a control gate over the retention layer;
- a tunneling layer over the control gate;
- a top gate over the tunneling layer;
- and
- a voltage source electrically coupled between the top gate and the control gate, wherein electrons generated by the voltage source have an energy level of lower than a conduction band of the retention layer.
6 more elements
A semiconductor device comprising:
- a substrate;
- a blocking layer over the substrate;
- a floating gate over the blocking layer, wherein the floating gate comprises a dielectric material;
- a retention layer over the floating gate;
- a control gate over the retention layer;
- a tunneling layer over the control gate;
- and
- a top gate over the tunneling layer.
5 more elements
Dependencies are inferred from the claim text.