Memory Array Buried Digit Line
AssigneeMicron Technology, Inc.
InventorDavid Wells
Life of this patent
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Abstract
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.
Claims25
A computer memory structure comprising:
- a plurality of active regions in a substrate, wherein the active regions are arranged in a plurality of columns;
- a trench in the substrate separating a first column from a second column of the plurality of columns of active regions;
- a digit line in the trench, wherein the digit line directly contacts the first column;
- and
- a filled asymmetric isolation window within the trench, wherein the isolation window separates the digit line from the second column.
An integrated circuit, comprising:
- a first elongated semiconductor ridge;
- a second elongated semiconductor ridge parallel to and spaced from the first ridge, the first and second ridges being separated by a trench, each of the first and second ridges serving as active areas for a plurality of transistors along the lengths of the ridges;
- a conductive line within the trench in continuous electrical contact with the first ridge;
- and
- an insulating element within the trench separating the conductive line from the second ridge.
Dependencies are inferred from the claim text.