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US 2008/0073676 A1Published application
Method for fabricating semiconductor device and semiconductor device
AssigneePanasonic Corporation
InventorShinji Takeoka
Life of this patent
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Abstract
An n-channel MOS transistor and a p-channel MOS transistor are formed on a semiconductor substrate 100. The p-channel MOS transistor includes a gate electrode 102a, a first offset sidewall 103a formed on side surfaces of the gate electrode 102a so as to contain fine particles 110 of group IV semiconductor therein. The n-channel MOS transistor includes a gate electrode 102b and a second offset sidewall 103b formed on side surfaces of the gate electrode 102b. After ion implantation of group IV semiconductor, heat treatment is performed to form the fine particles 110, so that a thickness of the first offset sidewall 103a can be made larger than a thickness of the second offset sidewall 103b.
Claims25
A semiconductor device comprising:
- a semiconductor substrate;
- a first MOS transistor including a first gate insulation film formed on a first region of the semiconductor substrate, a first gate electrode formed on the first gate insulation film, a first sidewall formed of an insulating material on each side surface of the first gate electrode, fine particles of group IV semiconductor crystal implanted at least in part of the first sidewall and a first impurity doped region of a first conductivity type formed in part of the first region located at a side of the first gate electrode and the first sidewall;
- and
- a second MOS transistor including a second gate insulation film formed on a second region of the semiconductor substrate, a second gate electrode formed on the second gate insulation film, a second sidewall formed of an insulating material on each side surface of the second gate electrode so as to have a smaller thickness than a thickness of the first sidewall and a second impurity doped region of a second conductivity type formed in part of the second region located at a side of the second sidewall.
1 more element
A method for fabricating a semiconductor device, the method comprising:
- a step a) of forming a first gate electrode on a first region of a semiconductor substrate with a first gate insulation film interposed therebetween and a second gate electrode on a second region of the semiconductor substrate with a second gate insulation film interposed therebetween;
- after the step a), a step b) of forming an insulating film over the semiconductor substrate;
- a step c) of selectively implanting ions of group IV semiconductor into part of the insulation film located on the first region;
- a step d) of performing heat treatment to the semiconductor substrate to form fine particles of group IV semiconductor in the part of the insulating film located on the first region;
- a step e) of removing part of the insulating film to form a first offset sidewall containing the fine particles implanted therein on each side surface of the first gate electrode and a second offset sidewall on each side surface of the second gate electrode;
- a step f) of selectively implanting ions of an impurity of a first conductivity type into the first region using the first gate electrode and the first offset sidewall as a mask to form a first extension region in each of parts of the first region located at both sides of the first gate electrode, respectively;
- and
- a step g) of selectively implanting ions of an impurity of a second conductivity type into the second region using the second gate electrode and the second offset sidewall as a mask to form a second extension region in each of parts of the second region located at both sides of the second gate electrode, respectively.
5 more elements
A method for fabricating a semiconductor device, the method comprising:
- a step a) of forming a first gate electrode on a first region of a semiconductor substrate with a first gate insulation film interposed therebetween and a second gate electrode on a second region of the semiconductor substrate with a second gate insulation film interposed therebetween;
- after the step a), a step b) of forming a first offset sidewall on each side surface of the first gate electrode and a second offset sidewall on each side surface of the second gate electrode;
- a step c) of selectively implanting ions of an impurity of a first conductivity type into the first region using the first gate electrode and the first offset sidewall as a mask to form a first extension region in each of parts of the first region located at both sides of the first gate electrode, respectively;
- a step d) of selectively implanting ions of an impurity of a second conductivity type into the second region using the second gate electrode and the second offset sidewall as a mask to form a second extension region in each of parts of the second region located at both sides of the second gate electrode, respectively;
- a step e) of forming a first insulating film over the semiconductor substrate;
- a step f) of selectively implanting ions of group IV semiconductor into part of the insulation film located on the first region;
- a step g) of performing heat treatment to the semiconductor substrate to form fine particles of group IV semiconductor crystal in the part of the first insulation film on the first region;
- a step h) of forming a second insulation film of a different material from a material of the first insulation film over the first insulation film;
- a step i) of removing parts of the first insulation film and the second insulation film to form a first doped region formation sidewall of the first insulation film as a base material on a side surface of the first offset sidewall and the semiconductor substrate so as to contain the fine particles implanted therein and have an L shape, a second doped region formation sidewall of the second insulation film as a base material on a side surface of the first doped region formation sidewall 1, a third doped region formation sidewall of the first insulation film as a base material on a side surface of the second offset sidewall and the semiconductor substrate so as to have an L shape and a fourth doped region formation sidewall of the second insulation film as a base material on a side surface of the second doped region formation sidewall.
6 more elements
Dependencies are inferred from the claim text.