Field-effect heterostructure transistors
AssigneeAlcatel-Lucent USA Inc.
InventorRobert L Willett
Life of this patent
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Abstract
An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located on one of the region and the layer and a gate electrode located to control a conductivity of a channel portion of the semiconductor heterostructure. The channel portion is located between the source and drain electrodes. The gate electrode is located vertically over the channel portion and portions of the source and drain electrodes.
Claims19
An apparatus, comprising:
- a field-effect transistor comprising:
- a region of first semiconductor;
- a layer of second semiconductor located on the region of the first semiconductor, the layer and region forming a semiconductor heterostructure;
- a source and drain electrodes located on one of the region and the layer;
- and
- a gate electrode located to control a conductivity of a channel portion of the semiconductor heterostructure, the channel portion being located between the source and drain electrodes, the gate electrode being located vertically over the channel portion and being located over portions of the source and drain electrodes.
A method, comprising:
- providing a semiconductor heterostructure;
- forming source and drain electrodes on the semiconductor heterostructure;
- depositing a dielectric layer over parts of the source and drain electrodes and over the part of the semiconductor heterostructure located between the source and drain electrodes;
- and
- forming a gate electrode vertically over the part of the semiconductor heterostructure between the source and drain electrodes and vertically over parts of the source and drain electrodes.
Dependencies are inferred from the claim text.