Tri-gate field-effect transistors formed by aspect ratio trapping

A method for forming a structure, the method comprising the steps of:

• forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material;
• defining a trench in the dielectric layer, the trench (i) extending to a surface of the substrate, and (ii) having a height h and a width w, the ratio of h to w being ≧0.5;
• forming, in the trench, at least one crystalline material layer comprising a second semiconductor material having a lattice mismatch with the first semiconductor material, a majority of dislocation defects in the second semiconductor material terminating within the trench;
• removing a portion of the dielectric layer to expose a side portion of the crystalline material;
• and
• defining a gate over the crystalline material.

A method for forming a structure, the method comprising:

• removing a portion of a semiconductor substrate comprising a first semiconductor material to define a fin;
• depositing a dielectric layer over the substrate and the fin;
• planarizing the dielectric layer such that a top surface thereof is substantially co-planar with a top surface of the fin;
• defining a trench by removing at least a portion of the fin, the trench having a height h and a width w, the ratio of h to w being ≧0.5;
• forming, in the trench, a crystalline material comprising a second semiconductor material lattice-mismatched to the first semiconductor material, a majority of dislocation defects in the crystalline material terminating within the trench;
• removing a portion of the dielectric layer to expose a side portion of the crystalline material;
• and
• defining a gate over the second semiconductor material.

A structure having a strained channel and including multiple semiconductor material layers at least partially disposed in a trench, the structure comprising:

• a dielectric layer disposed over a semiconductor substrate comprising a first semiconductor material;
• a trench disposed in the dielectric layer and (i) extending to a surface of the substrate, (ii) being defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate, and (iii) having a width w;
• a crystalline material at least partially disposed in the trench, the crystalline material including a first layer comprising a second semiconductor material and a second layer comprising a third semiconductor material, a side portion of the crystalline material extending above the dielectric layer;
• and
• a gate disposed over the crystalline material,
• wherein (i) a ratio of the height h to the width w is ≧0.5, (ii) a majority of dislocation defects in the crystalline material terminate at or below the predetermined distance H, (iii) h≧H, and (iv) the third semiconductor material defines a strained channel.

A semiconductor device including a transistor structure formed above a defect trapping region, the semiconductor device comprising:

• a defect trapping region comprising a trench including a dielectric sidewall, the defect trapping region being defined proximate a substrate having a first lattice constant;
• a semiconductor material disposed within the defect trapping region, the semiconductor material having a second lattice constant different from the first lattice constant, a majority of crystalline defects in the semiconductor material terminating within the defect trapping region;
• a fin having a semiconducting sidewall and a top surface, the fin being disposed above the semiconductor material disposed within the defect trapping region;
• and
• a transistor gate disposed over the semiconducting sidewall and the top surface.