Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures

A method for forming a structure, the method comprising:

• forming an opening above a region of a substrate comprising a first crystalline semiconductor material, the opening being defined by a dielectric sidewall and an exposed surface of the substrate;
• forming in the opening a second crystalline semiconductor material lattice-mismatched to the first crystalline semiconductor material;
• and
• defining a tunneling device over at least a portion of the second crystalline semiconductor material.

A structure integrating a tunneling diode and a transistor using lattice-mismatched materials, the structure comprising:

• a transistor formed proximate a substrate, the substrate including a first crystalline semiconductor material;
• and
• a tunneling diode coupled to one of a source or a drain of the transistor, the tunneling diode being disposed above a second crystalline semiconductor material lattice-mismatched to the first crystalline semiconductor material,
• wherein at least a portion of the second semiconductor material is disposed within an opening disposed above the substrate, the opening having a non-crystalline sidewall and configured to trap a majority of defects arising from the lattice mismatch between the first and second semiconductor materials.

A method of reducing SRAM circuit surface area, the method comprising:

• forming a resonant tunneling diode (RTD)-based static random access memory (SRAM) circuit, the RTD-based SRAM circuit having a perimeter defining an RTD-based SRAM cell area, the cell area including circuit components defining an SRAM memory cell, by:
• forming a transistor having a gate length above a substrate, the substrate including a first crystalline material, and
• forming at least one RTD proximate an opening disposed above the substrate, the opening comprising a non-crystalline sidewall, the RTD being coupled to a source or a drain of the transistor, the RTD including a crystalline material lattice-mismatched to the first crystalline material,
• wherein the RTD-based SRAM cell area is at least 33% smaller than a surface area of an SRAM circuit constructed using six transistors having the same gate length as the transistor in the RTD-based SRAM cell area.

A method of forming a transistor structure including a tunneling structure, the method comprising the steps of:

• forming an opening above a surface of a substrate comprising a first crystalline semiconductor material, the opening having a non-crystalline sidewall;
• forming a second crystalline semiconductor material in the opening, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material, a majority of defects arising from lattice-mismatch between the first and second semiconductor materials terminating within the opening;
• forming a tunneling structure over and in contact with at least a portion of the second crystalline semiconductor material;
• and
• forming first, second, and third terminals of a transistor proximate the tunneling structure.