Wide input common mode for input bias current cancellation
AssigneeNational Semiconductor Corporation
InventorKwok-Fu CHIU
Life of this patent
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Abstract
Described herein is technology for, among other things, input bias current cancellation. The technology includes a bipolar differential pair coupled with a supply voltage (VCC). The bipolar differential pair includes a first transistor and a second transistor. The technology further includes an input bias current cancellation circuit coupled with the bipolar differential pair and including a third transistor. The third transistor has a collector-emitter voltage VCE, and the bipolar differential pair is operable to receive an input voltage greater than VCC−2VCE without causing the third transistor to operate in the saturation region.
Claims22
A circuit, comprising:
- a bipolar differential pair coupled with a supply voltage (VCC) and comprising a first transistor and a second transistor;
- and
- an input bias current cancellation circuit coupled with said bipolar differential pair and comprising a third transistor, wherein said third transistor has a collector-emitter voltage VCE, and wherein further said bipolar differential pair is operable to receive an input voltage greater than VCC−2VCE without causing said third transistor to operate in the saturation region.
A circuit, comprising:
- a bipolar differential pair coupled with a supply voltage (VCC) and comprising a first transistor and a second transistor;
- and
- a input bias current cancellation circuit coupled with said bipolar differential pair and comprising a third transistor, wherein said third transistor has a collector-emitter voltage VCE, and wherein further said bipolar differential pair is operable to receive an input voltage up to VCC−VCE without causing said third transistor to operate in the saturation region.
A circuit for canceling input bias current for a bipolar differential pair, wherein said bipolar differential pair is driven by a first current generated by a first current source, said circuit comprising:
- a second current source for generating a second current that is proportional to said first current;
- a first transistor coupled with said second current source, wherein said second current source drives said first transistor;
- a base current sensing circuit coupled with said first transistor and for sensing a base current of said first transistor;
- and
- a current mirror coupled with said base current sensing circuit and said bipolar differential pair, said current mirror for mirroring said base current of said first transistor to bases of said bipolar differential pair.
A method for canceling input bias current for a bipolar differential pair, comprising:
- generating a second current that is proportional to a first current, wherein said first current drives said bipolar differential pair;
- biasing a transistor with said second current;
- and
- mirroring a base current of said transistor for bases of said bipolar differential pair.
Dependencies are inferred from the claim text.