Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip

A method for manufacturing a semiconductor integrated circuit device for enabling reference to manufacturing information unique to the semiconductor integrated circuit device through a measurement of the semiconductor integrated circuit device, characterized in that:

• said semiconductor integrated circuit device comprises a plurality of identification elements formed to have the same form as one another through the same manufacturing process as one another;
• said semiconductor integrated circuit device is measured at one timing during a process of manufacturing said semiconductor integrated circuit device to form first information which reflects a relation of magnitude in a physical amount of said plurality of identification elements to one another, said information being generated corresponding to variations in the physical amount of said plurality of identification elements;
• and
• said first information and second information including management information set in the manufacturing of said semiconductor integrated circuit device, which generates said first information, are held in an information holding device external to said semiconductor integrated circuit device as information unique to said semiconductor integrated circuit device,
• whereby from third information which is the same type of information as said first information, generated through a measurement of said semiconductor integrated circuit device at a timing different from said one timing, said first information corresponded to said third information within said information holding device is referenced from said third information, and said second information can be referenced from said first information which is referenced based on said third information.

A method for manufacturing a semiconductor integrated circuit device, characterized by comprising the steps of:

• forming a semiconductor integrated circuit device comprising a first chip, said semiconductor integrated circuit device having a plurality of identification elements formed to have the same form as one another and formed through the same manufacturing process as one another;
• retrieving unique identification information from said plurality of identification elements in said semiconductor integrated circuit device comprising said first chip;
• writing a plurality of unique identification information from said semiconductor integrated circuit device comprising said first chip, and operation modification information for said semiconductor integrated circuit device which provides the respective unique identification information, into a second chip;
• and
• integrally assembling said first chip and second chip,
• wherein said assembled second chip is configured to output said operation modification information to said first chip based on the unique identification information retrieved from said first chip integrally assembled therewith.

A method for manufacturing a semiconductor integrated circuit device, characterized by using a soft IP technique to design and layout an identification number circuit including:

• an identification element sequence comprised of a plurality of unit elements each including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of said first inverter circuit, and a second switch disposed at the input terminal of said first inverter circuit, said unit elements being arranged in cascade through said second switch;
• an amplifier circuit including a second inverter circuit having an input terminal connected to the output terminal of said first inverter circuit corresponded to a final stage of said identification element sequence;
• and
• a shift register having shift bits corresponding to said first switch and said second switch of each said first inverter in said identification element sequence,
• wherein said identification number circuit is responsive to a shift operation of said shift register to sequentially turn on said first switches in said identification elements from the first circuit and turn off said second switches complementarily to said first switches to receive a plurality of identification information corresponding to said respective first inverter circuits in said identification element sequence from output signals of said amplifier circuit including said third inverter circuit to generate an identification number.

A method for tracing information including particulars for an integrated circuit device having an identification information generation circuit, comprising the steps of:

• (a) performing, at a first time of manufacturing the integrated circuit device, the steps of:
• (a1) performing a measurement with respect to an intermediate product of said integrated circuit device to provide information including particulars relating to said intermediate product;
• (a2) activating said identification information generation circuit to perform detection of information which reflects variations in electric parameters of said logic circuits caused during said manufacturing process, and outputting the identification information;
• and
• (a3) storing in a storage means said information including particulars with respect to the intermediate product provided by said measurement in step (a1) by relating said information to said identification information derived by step (a2) as a reference;
• and
• (b) performing, at a second time later than said first time, the steps of:
• (b1) activating said identification information generation circuit to perform step (a2) and outputting the identification information;
• and
• (b2) retrieving from said storage means the stored information using the identification information derived by step (b1) as the reference.

A method for tracing information including particulars of an integrated circuit device, the method comprising the steps of:

• (a) preparing a semiconductor wafer on which a plurality of integrated circuit chip areas is formed, each said chip area formed with an identification information generation circuit including a plurality of identification elements formed within one chip area, said identification elements each including a logic circuit having the same form and constructed according to the same manufacturing process and configured to output, when the identification information generation circuit is activated, information which is indicative of variations caused in electrical characteristics of said plurality of logic circuits during said manufacturing process;
• (b) performing at the first time of step (a), the steps of:
• (b1) performing a measurement with respect to each of said plurality of integrated circuits to provide information including particulars relating to the respective integrated circuits;
• (b2) activating said identification information generation circuit on respective chip areas to output the identification information which is indicative of variations in electrical characteristics of said plurality of logic circuits caused within the respective chip areas during said manufacturing process;
• and
• (b3) storing in storage means the information including particulars of the integrated circuits provided by said measurement in step (b1) by relating said information to the corresponding identification information derived by step (b2) as the reference, respectively;
• and
• (c) performing, at a later second time wherein said chip areas are separated from said wafer and assembled as individual integrated circuit devices with respect to one of the assembled integrated circuit devices, the steps of:
• (c1) activating said identification information generation circuit to output the identification information which is indicative of variations in electrical characteristics of said plurality of logic circuits caused within the chip areas during said manufacturing process;
• and
• (c2) retrieving from said storage means the stored information with respect to the assembled integrated circuit device using the identification information derived by step (c1) as the reference.