# US 2008/0002473 A1 · Two terminal memory array having reference cells

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2008/0002473 A1
- Document ID: US20080002473A1
- Status: Published application
- Kind: A1
- Application number: 11/707,340
- Filed: 2007-02-16
- Published: 2008-01-03
- Earliest claimed: 2006-06-29
- Assignees: Unity Semiconductor Corporation
- Inventors: Darrell Rinerson; Christophe Chevallier; Steven Longcor
- Web page: https://patentgrep.com/patent/US20080002473A1

## CPC

- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2213/31: Material having complex metal oxide, e.g. perovskite structure
- G11C 2213/71: Three dimensional array
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

## Claims

### Claim 1

A memory comprising:
a substrate including address lines and active circuitry, the active circuitry including sensing circuitry and address decoding circuitry, the address decoding circuitry in communication with the address lines;
addressable two-terminal memory plugs that are activated by the address decoding circuitry, each two-terminal memory plug operable to be reversibly written to a first resistive state at a first write voltage, reversibly written to a second resistive state at a second write voltage, and have its resistive state determined at a read voltage; and
at least one reference cell that contributes to a reference level, wherein the sensing circuitry is operative to produce an output that is a function of the resistive state of the activated two-terminal memory plug and the reference level, wherein the at least one reference cell is similar in structure to the two-terminal memory plugs,
wherein the addressable two-terminal memory plugs and the at least one reference cell are positioned over the substrate.

### Claim 2 (depends on 1)

The memory of claim 1, wherein the reference level has an effective resistance that is intermediate to the first resistive state and the second resistive state.

### Claim 3

A memory comprising:
a substrate including address lines and active circuitry, the active circuitry including sensing circuitry and address decoding circuitry, the address decoding circuitry in communication with the address lines;
addressable two-terminal memory plugs that are activated by the address decoding circuitry, each two-terminal memory plug operable to be reversibly written to a first resistive state at a first write voltage, reversibly written to a second resistive state at a second write voltage, and have its resistive state determined at a read voltage; and
a reference level, wherein the sensing circuitry is operative to produce an output that is a function of the resistive state of the activated two-terminal memory plug and the reference level, and
wherein the addressable two-terminal memory plugs are positioned over the substrate.

### Claim 4

A method of programming a reference cell, comprising:
providing a substrate that includes active circuitry, a two-terminal memory array positioned over the substrate, and at least one reference cell positioned outside of the two-terminal memory array and over the substrate; and
applying a programming voltage across a first terminal and a second terminal of the at least one reference cell, the applying operative to change a programmable resistance of the at least one reference cell to a desired value.