Method for treating design errors of a layout of an integrated circuit
OwnerMarkus Hofsaessinventor
Life of this patent
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Abstract
Embodiments of the invention provide a method for treating errors during the checking of a design of an integrated circuit. In one embodiment, the method includes checking the design of the integrated circuit for errors using predetermined design rules, wherein the design includes a plurality of cells, detecting a design error when the design deviates from the predetermined design rules, writing the design error into a design error file, wherein at least one detected design error is written into a design waiver file if the design error is allowed as an allowed design error in spite of the deviation from the predetermined rules, and storing the allowed design error in the design waiver file with specification of a cell in which the design error occurs.
Claims20
A method for treating errors during the checking of a design of an integrated circuit, comprising:
- checking the design of the integrated circuit for errors using predetermined design rules, wherein the design includes a plurality of cells;
- detecting a design error when the design deviates from the predetermined design rules;
- writing the design error into a design error file, wherein at least one detected design error is written into a design waiver file if the design error is allowed as an allowed design error in spite of the deviation from the predetermined rules;
- and
- storing the allowed design error in the design waiver file with specification of a cell in which the design error occurs.
The method as claimed in claim 3, further comprising:
- creating a layout waiver file for the plurality of cells, wherein the layout waiver file comprises allowed layout errors of the cell, and wherein the layout waiver file comprises data describing a type of the layout error, a position of the layout error in the cell, and data on a position of the cell with regard to the layout.
The method of 1, further comprising:
- storing error files for allowed errors in a memory;
- and
- for each of the plurality of cells, creating a waiver file which describes error files of allowed errors which are contained in the cell.
A tangible, computer-readable medium containing instructions, which, when executed by a processor, are configured to perform method for treating errors during the checking of a design of an integrated circuit, the method comprising:
- checking the design of the integrated circuit for errors using predetermined design rules, wherein the design includes a plurality of cells;
- detecting a design error when the design deviates from the predetermined design rules;
- writing the design error into a design error file, wherein at least one detected design error is written into a design waiver file if the design error is allowed as an allowed design error in spite of the deviation from the predetermined rules;
- and
- storing the allowed design error in the design waiver file with specification of a cell in which the design error occurs.
A computer system comprising:
- a memory including a design of an integrated circuit;
- a processor configured to:
- check the design of the integrated circuit for errors using predetermined design rules, wherein the design includes a plurality of cells;
- detect a design error when the design deviates from the predetermined design rules;
- write the design error into a design error file, wherein at least one detected design error is written into a design waiver file if the design error is allowed as an allowed design error in spite of the deviation from the predetermined rules;
- and
- store the allowed design error in the design waiver file with specification of a cell in which the design error occurs.
Dependencies are inferred from the claim text.