Combined encoder/syndrome generator with reduced delay
AssigneeHitachi Global Technologies Netherlands B.V.
InventorsMartin Hassner, Kirk Hwang
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Abstract
A combined encoder/syndrome generator is provided that has a reduced delay. The combined encoder/syndrome generator generates check symbols during an encoding process and error syndromes during a decoding process. The combined encoder/syndrome generator has two or more blocks. The output of each block is fed as an input into a subsequent block. Each block can perform computations in parallel to reduce the delay of the encoding system.
Claims20
A combined encoder/syndrome generator comprising:
- a first adder chain topology coupled to receive an input sequence and generating syndromes during a decoding mode;
- a second adder chain topology coupled to receive the input sequence generating syndromes during the decoding mode,
- wherein the first and the second adder chain topologies generate separate outputs in parallel that are used to generate check symbols during an encoding mode, and a current output of the second adder chain topology is dependent on a prior output of the first adder chain topology.
A combined encoder/syndrome generator circuit comprising:
- a first adder chain circuit block coupled to receive an input sequence, the first adder chain circuit block comprising first adder stages that generate syndromes during a decoding mode;
- a second adder chain circuit block coupled to receive the input sequence, the second adder chain circuit block comprising second adder stages that generate syndromes during the decoding mode,
- wherein the first and the second adder chain circuit blocks generate separate outputs in parallel that are used to generate check symbols during an encoding mode, and a current output of the second adder chain circuit block is dependent on a previous output of the first adder chain circuit block.
A method for generating check symbols and error syndromes using a combined encoder/syndrome generator, the method comprising:
- generating error syndromes during a decoding mode using a first adder chain block that receives an input sequence;
- generating error syndromes during the decoding mode using a second adder chain block that receives the input sequence;
- and
- generating check symbols during an encoding mode using the first and the second adder chain blocks, wherein the first and the second adder chain blocks generate separate outputs in parallel during the encoding mode, and a current output of the second adder chain block is dependent on a previous output of the first adder chain block.
Dependencies are inferred from the claim text.