Cyclic redundancy check (CRC) based error correction method and device
AssigneeHarris Corporation
InventorsJohn Nieto, William Furman
Life of this patent
Estimating the term…
Abstract
The communication method includes the use of CRC codes for additional error correaction in addition to the error detection capability. The method is for error detection and correaction in a received message that includes N message bits and M Cyclic Redundancy Check (CRC) bits appended thereto. It is determined whether at least one bit error has occurred in the N message bits and M CRC bits of the received message based upon the M CRC bits, and when at least one bit error is determined, then K bits with a lowest quality metric are selected from the N message bits and M CRC bits. The bit error is corrected based upon possible bit error patterns and the selected K bits. Multiple bit errors may also be corrected.
Claims25
A method for error detection and correaction in a received message comprising N message bits and M Cyclic Redundancy Check (CRC) bits appended thereto, the method comprising:
- determining whether at least one bit error has occurred in the N message bits and M CRC bits of the received message based upon the M CRC bits;
- when at least one bit error is determined, then selecting, from the N message bits and M CRC bits, K bits with a lowest quality metric;
- and
- correcting the at least one bit error based upon possible bit error patterns and the selected K bits.
A method for error detection and correaction in a received message comprising N message bits and M Cyclic Redundancy Check (CRC) bits appended thereto, the method comprising:
- determining whether an error has occurred in the N message bits and M CRC bits of the received message based upon at least the M CRC bits;
- determining whether the error is a multiple-bit error based upon a failure to match a CRC value with possible single-bit error patterns stored in a table;
- when a multiple-bit error is determined, then selecting, from the N message bits and M CRC bits, K bits with a lowest quality metric;
- and
- correcting the error based upon a logical combination of a plurality of the single bit error patterns and the selected K bits.
A communications device comprising:
- an input for receiving a message comprising N message bits and M Cyclic Redundancy Check (CRC) bits appended thereto;
- a error detection and correaction block connected to said input for determining whether at least one bit error has occurred in the N message bits and M CRC bits of the received message based upon at least the M CRC bits, and when at least one bit error is determined, then selecting, from the N message bits and M CRC bits, K bits with a lowest quality metric, and correcting the at least one bit error based upon possible bit error patterns and the selected K bits;
- and
- an output connected to said error detection and correaction block for outputting the corrected message.
Dependencies are inferred from the claim text.