Semiconductor device and method of adding tester circuit for the same
AssigneeNEC Electronics Corporation
InventorMasakazu Maehara
Life of this patent
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Abstract
A semiconductor device according to an embodiment of the present invention includes: a plurality of clock domains including a plurality of logic circuits operating in accordance with a clock signal; and a control circuit selectively supplying the clock signal to a predetermined number of clock domains selected from the plurality of clock domains based on a control signal.
Claims20
A semiconductor device comprising:
- a plurality of clock domains including a plurality of logic circuits operating in accordance with a clock signal;
- and
- a control circuit selectively supplying the clock signal to a predetermined number of clock domains selected from the plurality of clock domains based on a control signal.
A program product causing a computer to execute a procedure of designing a tester circuit of a semiconductor device including a plurality of clock domains including a plurality of logic circuits operating in accordance with a clock signal, the procedure comprising:
- reading first circuit information prior to insertion of the tester circuit and second circuit information representing a frequency of the clock signal supplied to the clock domain, and grouping clock domains to be tested as first groups with the clock signals of the same frequency among the plurality of clock domains;
- grouping clock domains having no data-path-based interdependence as second groups among the clock domains in the first group, and adding to the first circuit information, information about control circuits corresponding to the first groups, supplying the clock signal to each of the first groups, and distributing the control signals to the second groups based on a control signal.
A method of adding a tester circuit that adds a tester circuit to a semiconductor device including a plurality of clock domains including a plurality of logic circuits operating in accordance with a clock signal by use of a computer, comprising:
- inputting first circuit information prior to insertion of the tester circuit;
- deriving test frequency information of a clock domain based on second circuit information representing a frequency of the clock signal supplied to the clock domain;
- extracting data-path-based interdependence representing how clock domains transmit/receive data to/from each other based on the first circuit information;
- deriving information about a plurality of first groups obtained by grouping a predetermined number of clock domains based on the first circuit information and the test frequency information;
- deriving information about a plurality of second group obtained by grouping clock domains operating independently of each other in one first group based on the data-path-based interdependence and the information about the first group;
- and
- adding to the first circuit information, information about a control circuit including output terminals of the clock signal as many as the second subgroups in the connected first group, and controlling a clock domain to which the input clock signal is supplied, for each of the second groups.
Dependencies are inferred from the claim text.