Shift register, scan driving circuit and display device having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Jae KANG, Seoung-Bum PYOUN
Life of this patent
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Abstract
A shift register includes a plurality of stages, each of the stages generate an output signal, in sequence. Each of the shift register includes a present stage and a first capacitor. The present stage outputs an output signal based on one of a scan start signal and a carry signal of the previous stage. The first capacitor reduces a ripple component of the carry signal of the present stage which activates the next stage. Therefore, a carry signal having a reduced ripple component is supplied to the next stage, so that a transient current is intercepted at a transistor receiving the carry signal, which is arranged in the next stage, thus ensuring reliability of the shift register.
Claims14
A shift register having a plurality of stages in which each of the stages generate an output signal in sequence, the shift register comprising:
- a present stage;
- a next stage following the present stage, the present stage outputting an output signal based on one of a scan start signal and a carry signal of a previous stage to the next stage;
- and
- a first capacitor reducing a ripple component of the carry signal of the present stage and activating a next stage.
A scan driving circuit comprising a plurality of stages connected to each other, a first stage of the plurality of stages includes an input terminal into which a scan start signal is inputted, each of the stages receives at least one of a first clock signal and a second clock signal having a phase opposite to the first clock signal, and
- each of the stages outputting an output signal to the gate lines based on one of a scan start signal and a carry signal of a previous stage,
- wherein the stages comprise a first capacitor arranged between adjacent stages, the first capacitor reducing a ripple component of the carry signal outputted from the present stage to activate a next stage.
A display device comprising:
- a cell array circuit formed on a substrate, the cell array circuit having a plurality of data lines and a plurality of gate lines, and each of the cell array circuits being connected to a corresponding pair of data lines and gate lines;
- and
- a scan driving circuit formed on the substrate, the scan driving circuit having a shift register including a plurality of stages connected to each other, the stages having a first stage with an input terminal into which a scan start signal is inputted, for sequentially selecting the gate lines based on an output signal of each stage, and the stages receiving at least one of a first clock signal and a second clock signal having a phase opposite to the first clock signal, and
- each of the stages outputting an output signal to the gate lines based on one of a scan start signal and a carry signal of a previous stage,
- wherein the shift register comprises a first capacitor arranged between adjacent stages, the first capacitor reduces a ripple component of the carry signal outputted from a present stage to activate a next stage.
Dependencies are inferred from the claim text.