US 2007/0192658 A1 · Measuring the internal clock speed of an integrated circuit

Abstract

A system and methods to transfer data between a testing interface and an IC. The system may include a synchronization subsystem to monitor the transitions of the test interface clock and/or IC clock to determine a clock adjustment appropriate to substantially synchronize the clocks. In certain implementations, a synchronization unit on an IC under test counts a predetermined number of transitions of an internal clock of an embedded device and generates a signal upon reaching a terminal count, which signal is received by a host controller associated with a JTAG test fixture. In such implementations, the host controller determines the number of IC clock cycles that occurred during the predetermined number of IC clock cycles and synthesizes a synchronized JTAG clock that is a integral fraction of the IC clock.

Claims26

Dependent claims

A method to synchronize a serial access port clock with a clock of a device under test, the method comprising:

identifying at least an approximate number of transitions of the serial access port clock, the approximate number of transitions occurring during a first period;
identifying at least an approximate number of transitions of the device clock that occur during a time period substantially equal to the first period;
synchronizing the serial access port clock and the device clock based on the identified number of transitions of the device clock and the identified number of transitions of the serial access port clock.

Dependencies are inferred from the claim text.

Measuring the internal clock speed of an integrated circuit

Life of this patent

Measuring the internal clock speed of an integrated circuit

Life of this patent

Abstract

Claims26