Minimum processor instruction for implementing weighted fair queuing and other priority queuing
AssigneeConexant Systems, Inc.
InventorsBoris Zabarski, David Sitbon, Oded Norman
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Abstract
The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).
Claims12
A processor for determining a minimum value of a plurality of values stored in source registers and determining an index value of source register having the minimum value, the processor comprising:
- means for determining a first minimum value of a first value and a second value;
- means for determining a second minimum value of a third value and a fourth value;
- means for storing the first minimum value in a first portion of a first destination register and the second minimum value in a second portion of the first destination register;
- and
- means for storing a first index value associated with the first minimum value in a first portion of a second destination register and a second index value associated with the second minimum value in a second portion of the second destination register;
- wherein the means for determining the first minimum value and the means for determining the second minimum value are adapted to execute in parallel.
A processor for determining a maximum value of a plurality of values stored in source registers and determining an index value of source register having the maximum value, the processor comprising:
- means for determining a first maximum value of a first value and a second value;
- means for determining a second maximum value of a third value and a fourth value;
- means for storing the first maximum value in a first portion of a first destination register and the second maximum value in a second portion of the first destination register;
- and
- means for storing a first index value associated with the first maximum value in a first portion of a second destination register and a second index value associated with the second maximum value in a second portion of the second destination register;
- wherein the means for determining the first maximum value and the means for determining the second maximum value are adapted to execute in parallel.
Dependencies are inferred from the claim text.