Programmable processing unit providing concurrent datapath operation of multiple instructions

A system, comprising:

• an Ethernet MAC (media access controller);
• and
• a processor comprising:
• multiple programmable processor cores;
• and
• multiple processing units, each of the processing units, comprising:
• a datapath comprising an input buffer, at least one memory and an arithmetic logic unit;
• and
• control logic having access to a program instruction control store, the control logic to control operation of the datapath, the control logic to concurrently cause the datapath to operate in response to different instructions that use different sections of the datapath, wherein the different sections of the datapath comprise a first section transferring data from the input buffer to the memory and a second section transferring data from the memory to the arithmetic logic unit.