Reverse polish notation processing device, and electronic integrated circuit including such a processing device

An electronic integrated circuit comprising a Reverse Polish notation processing device, allowing to execute a set of instructions wherein each instruction comprises N operands at most, where N≧1, said processing device implementing management of a stack whose size is variable, wherein the processing device comprises:

• a storage device including a random access memory and a cache memory;
• a stack pointer managing device, that manages a stack pointer, which is a physical address, in said random access memory, associated with a reference stage of the stack, each stage of the stack being associated with a physical address, in said random access memory, which varies according to the stack size;
• and
• a contents managing device, which manages the contents of the stages of the stack, according to said stack pointer:
• such that, for each of the first N stages of the stack, the content of said stage is stored in said cache memory, and for each of the other stages of the stack, the content of said stage is stored in said random access memory, at the physical address associated with said stage;
• and
• allowing the content managing device to manage content overflows from the cache memory towards the random access memory, and vice-versa.