US 2007/0192568 A1 · Thread optimized multiprocessor architecture

Abstract

In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors; wherein each of the processors is operable to process a de minimis instruction set, and wherein each of the processors comprises local caches dedicated to each of at least three specific registers in the processor. In another aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors, wherein each of the processors is operable to process an instruction set optimized for thread-level parallel processing.

Claims24

Dependent claims

A system comprising:

a plurality of parallel processors on a single chip;
and
computer memory located on said chip and accessible by each of said processors,
wherein each of said processors is operable to process a de minimis instruction set, and
wherein each of said processors comprises local caches dedicated to each of at least three specific registers in said processor.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/702,979Filed 5 Feb 2007

Priority

3 Feb 2006

Published

16 Aug 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/30138
Organisation of register space, e.g. banked or distributed register file: extension of register space, e.g. register cache
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/322
Address formation of the next instruction, e.g. by incrementing the instruction counter: for non-sequential address

Abstract

Facts

Application

11/702,979Filed 5 Feb 2007

Priority

3 Feb 2006

Published

16 Aug 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/30138
Organisation of register space, e.g. banked or distributed register file: extension of register space, e.g. register cache
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/322
Address formation of the next instruction, e.g. by incrementing the instruction counter: for non-sequential address

Thread optimized multiprocessor architecture

Life of this patent

Abstract

Claims24

Thread optimized multiprocessor architecture

Life of this patent

Abstract

Claims24