Programmable processing unit

A system, comprising:

• an Ethernet MAC (media access controller);
• a processor coupled to the Ethernet MAC, the processor comprising:
• multiple processor cores;
• and
• multiple processing units, each of the multiple processing units comprising:
• an input buffer to store data received by the processing unit;
• a memory, coupled to the input buffer;
• an arithmetic logic unit coupled to the input buffer and to the memory, the arithmetic logic to perform operations on operands provided by the input buffer and the memory;
• an output buffer coupled to the arithmetic logic unit and the memory to store data to transfer from the processing unit;
• and
• control logic having access to a control store of program instructions, the control logic to process instructions including:
• an instruction to transfer data from the input buffer to the memory;
• an instruction cause the arithmetic logic unit to perform an operation on operands provided by both the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.