Microarchitectural wire management for performance and power in partitioned architectures

A method for routing traffic between a cluster element and a cache in a processor, said method comprising:

• providing a processor having a cluster element and a cache, said cluster element connected to said cache using an interconnect having a plurality of conductor means;
• determining, at said cluster element, the address of a requested data block to be retrieved from said cache;
• transmitting a plurality of first selected bits comprising a subset of said address from said cluster element to said cache on a first conductor means associated with said interconnect;
• retrieving a plurality of data cache blocks including said data block out of said cache, said plurality of data cache blocks corresponding to said plurality of first selected bits;
• transmitting a plurality of second selected bits comprising said address of said requested data block from said cluster element to said cache on a second conductor means associated with said interconnect;
• identifying said requested data block from said plurality of data cache blocks using said plurality of second selected bits;
• and
• transmitting said requested data block from said cache to said cluster element.

A method for routing traffic from a cluster element over a low bandwidth, low latency interconnect in a processor, said method comprising:

• identifying, at said cluster element, a narrow bit-width data element having a plurality of identifying information and a plurality of bits of data to be transported from said cluster element over said low bandwidth, low latency interconnect;
• determining if said plurality of bits of data may be transmitted on a first conductor associated with said low bandwidth, low latency interconnect based upon the size of said plurality of bits of data;
• transmitting said plurality of identifying information on a second conductor associated with said low bandwidth, low latency interconnect;
• and
• transmitting said plurality of bits of data on said first conductor associated with said low bandwidth, low latency interconnect.

A method for routing traffic in a multi-processor environment, said method comprising:

• providing at least a first processor element having a first processor cache connected thereto, a second processor element having a second processor cache connected thereto and a back-up L2 cache;
• providing a first interconnect having a first plurality of conductors, said first interconnect connected to extend from said first processor cache to said back-up L2 cache;
• providing a second interconnect having a second plurality of conductors, said second interconnect connected to extend from said second processor cache to said back-up L2 cache;
• providing a third interconnect having a third plurality of conductors, said third interconnect connected to extend from said first processor cache to said second processor cache;
• transmitting critical data on latency optimal conductors from said plurality of conductors from said first, second and third interconnect using a directory-based cache coherence protocol;
• and
• transmitting non-critical data on low power, high bandwidth conductors from said plurality of conductors from said first, second and third interconnect using said directory-based cache coherence protocol.

A method for routing traffic in a multi-processor environment, said method comprising:

• providing at least a first processor element having a first processor cache, a second processor element having a second processor cache, a back-up L2 cache and a bus, said first processor cache, said second processor cache and said back-up L2 cache being connected to said bus;
• providing at least one interconnect on said bus, said interconnect having a plurality of conductors;
• transmitting at least one control signal on a latency optimal conductor on said bus using a snooping-based cache coherence protocol;
• and
• transmitting data on low power, high bandwidth conductor from said plurality of conductors on said bus using said a snooping-based cache coherence protocol.