Architectural support for thread level speculative execution
AssigneeInternational Business Machines Corporation
InventorsAlan Gara, Valentina Salapura
Life of this patent
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Abstract
A method and apparatus for hardware support of the thread level speculation for existing processor cores without having to change the existing processor core, processor core's interface, or existing caches on the L1, L2 or L3 level. Architecture support for thread speculative execution by adding a new cache level for storing speculative values and a dedicated bus for forwarding speculative values and control. The cache level is hierarchically positioned between the cache levels L1 and L2 cache levels.
Claims35
An apparatus for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes, each processing unit having first and second level caches operatively connected therewith for enabling multiprocessing, the apparatus comprising:
- an additional cache level local at each said processing unit for use only in a thread level speculation mode, each said additional cache for storing speculative results and status associated with its associated processor when handling speculative threads;
- means for interconnecting each said additional cache level for forwarding speculative values and control data between parallel executing threads;
- and
- means for bypassing said additional cache level when no speculation processing thread is enabled at an associated processing unit.
A method for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes, each processing unit having first and second level caches operatively connected therewith for enabling multiprocessing, the method comprising providing an additional local cache level at each said processing unit for use only in a thread level speculation mode, each said additional cache for storing speculative results and status associated with its associated processor when handling speculative threads.
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes, each processing unit having first and second level caches operatively connected therewith for enabling multiprocessing, the method steps comprising:
- providing an additional local cache level at each said processing unit for use only in a thread level speculation mode, each said additional cache for storing speculative results and status associated with its associated processor when handling speculative threads.
Dependencies are inferred from the claim text.