Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorKoichi Fukuda
Life of this patent
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Abstract
A semiconductor device includes an electrical circuit formed on a substrate; a level detector outputting a first level signal which has a signal level based on power supply voltage and which determines an operation of the electrical circuit; a command decoder decoding a command that is inputted from the outside, and outputting a command signal; a control circuit to which the command signal is inputted, the control circuit outputting a state signal expressing whether the electrical circuit is in an operation state; and a first latch circuit to which the first level signal and the state signal are inputted, the first latch circuit latching the first level signal at a time based on the state signal.
Claims16
A semiconductor device comprising:
- a level detector configured to output a first flag signal and a second flag signal, the first flag signal indicating that a power supply voltage surpasses a first threshold, the second flag signal indicating that the power supply voltage surpasses a second threshold higher than the first threshold;
- a first latch circuit configured to latch the first and the second flag signals at a time when both logic levels of the first and the second flag signals become same, and to generate the first level signal based on the first and the second flag signals;
- and
- a second latch circuit to which the first level signal and a state signal are inputted, the state signal expressing whether an electrical circuit is in an operation state, the second latch circuit configured to latch the first level signal at a time based on the state signal and to generate a second level signal which determines an operation of the electrical circuit.
A semiconductor device comprising:
- a level detector configured to output a first level signal which makes a level transition when a power supply voltage exceeds a first threshold and when the power supply voltage falls below the first threshold;
- and
- a first latch circuit to which the first level signal and a state signal are inputted, the state signal expressing whether an electrical circuit is in an operation state, the first latch circuit configured to latch the first level signal and generating a second level signal which determines an operation of the electrical circuit, wherein
- the first latch circuit is configured to latch the first level signal at a time when the first level signal makes transition in a case that the power supply voltage surpasses the first threshold, and to latch the first level signal at a time based on the state signal in a case that the power supply voltage is lower than the first threshold.
Dependencies are inferred from the claim text.