Packed add-subtract operation in a microprocessor

A method of executing a packed half-word addition and subtraction operation in a single operational cycle of a processor circuit, the method comprising:

• selecting a first operand from a designated top or bottom half-word of a designated first source register of a register file;
• selecting a second operand from a designated top or bottom half-word of a designated second source register of the register file, the designated second source register not necessarily the same as the designated first source register;
• performing respective half-word addition and half-word subtraction of the selected first and second operands in parallel in a single operational cycle of the processor circuit;
• and
• providing a sum and difference resulting from the parallel half-word addition and half-word subtraction operation to respective top and bottom half-word locations of a designated destination register of the register file.

A method of performing an efficient butterfly computation in a processor circuit upon complex values a, b and ci, with real and imaginary components of the complex values being half-word values packed into half-word portions of a register file, the method comprising:

• performing a series of operations in the microprocessor upon the half-word components of the complex values b and ci to obtain half-word real and imaginary components of a complex temporary value tmp, such that
• Re(tmp):=Re(b)Re(ci)−Im(b)Im(ci);
• and (1)
• Im(tmp):=Re(b)Im(ci)+Im(b)Re(ci);
• (2)
• performing a first packed half-word addition and subtraction operation in parallel upon the half-word real components of the complex values a and tmp to obtain half-word real components of complex values A and B, such that
• Re(A):=Re(a)+Re(tmp);
• and (1)
• Re(B):=Re(a)−Re(tmp);
• (2)
• wherein the real components of a and tmp are obtained from selected top or bottom half-word locations of designated, not necessarily the same, first and second source registers of the register file, and the resulting sum and difference obtained thereby representing the real components of A and B are packed into respective top and bottom half-word locations of a designated first destination register;
• and
• performing a second packed half-word addition and subtraction operation in parallel upon the half-word imaginary components of the complex values a and tmp to obtain half-word imaginary components of the complex values A and B, such that
• Im(A):=Im(a)+Im(tmp);
• and (1)
• Im(B):=Im(a)−Im(tmp);
• wherein the imaginary components of a and tmp are obtained from selected top or bottom half-word locations of designated, not necessarily the same, third and fourth source registers of the register file, and the resulting sum and difference obtained thereby representing the imaginary components of A and B are packed into respective top and bottom half-word locations of a designated second destination register different from said first destination register.