Device and method to eliminate shorting induced by via to metal misalignment
AssigneeAgere Systems Inc.
InventorsRanbir Singh, Sen Sidhartha, Nace Rossi
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Abstract
The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.
Claims13
An semiconductor device interconnect, comprising:
- a metal line located over a substrate;
- a dielectric layer located over said metal line;
- and
- an interconnect located in said dielectric layer, including a landed portion located over said metal line and an unlanded portion located along at least a portion of a lateral edge of said metal line, said unlanded portion being at least partially filled with a polymer and said landed portion being substantially filled with a conductive material.
An integrated circuit comprising:
- active devices located over a semiconductor substrate;
- dielectric layers located over said active devices;
- metal lines located over said active devices;
- and
- interconnects located in said dielectric layers, wherein at least one of said interconnects includes a landed portion located over one of said metal lines and an unlanded portion located along at least a portion of a lateral edge of said at least one of said metal lines, said unlanded portion being at least partially filled with a polymer and said landed portion being substantially filled with a conductive material, said interconnects interconnecting said active devices to form an operative integrated circuit.
Dependencies are inferred from the claim text.