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US 2007/0190776 A1Published application
Methods of Processing Thick ILD Layers Using Spray Coating or Lamination for C4 Wafer Level Thick Metal Integrated Flow
AssigneeIntel Corporation
InventorsSarah Kim, Kevin Lee, Steven Towle, Anna George
Life of this patent
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Abstract
A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.
Claims17
A method comprising:
- forming microelectronic circuitry in a generally planar semiconductor die, the microelectronic circuitry including a collection of conductive nodes;
- electrodepositing a thick metal line oriented to cross the semiconductor die and to be in electrical contact with two or more conductive nodes in the collection, wherein the thick metal line has a thickness in excess of 1 micrometer;
- and
- spray coating an electrically insulating dielectric layer to cover the thick metal line.
1 more element
A method comprising:
- forming microelectronic circuitry in a generally planar semiconductor die, the microelectronic circuitry including a collection of conductive nodes;
- electrodepositing a thick metal line oriented to cross the semiconductor die and to be in electrical contact with two or more conductive nodes in the collection, wherein the thick metal line has a thickness in excess of 1 micrometer;
- and
- laminating an electrically insulating dielectric layer to cover the thick metal line.
1 more element
Dependencies are inferred from the claim text.