Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same

A process comprising:

• mating a microelectronic die substrate to a board, wherein the substrate includes an upper surface, a lower surface, and a solder first bump disposed on the lower surface, wherein the solder first bump is selected from:
• 36%-indium-63%;
• 28%-tin-48%;
• and 2%-bismuth 26%;
• 42%-bismuth-62%;
• 19%-tin-42%;
• and 7%-indium 28%;
• 33%-indium-67%;
• 32%-bismuth-67%;
• and 0.1%-tin-20%;
• 52%-indium-54% indium;
• 0.01%-zinc-2%;
• and 46%-tin-48%;
• or
• 33%-indium-67%;
• 32%-bismuth-67%;
• and 0.1%-zinc-1%;
• forming a stress-compensation collar (SCC) on the board during mating the die and the board, wherein the SCC abuts the solder first bump;
• and
• reflowing the solder first bump wherein the solder includes at least one doping element, wherein reflowing includes in situ alloying of the at least one doping element.

An article comprising:

• a mounting substrate including a lower surface and an upper surface;
• a solder first bump disposed on the lower surface, wherein the solder first bump is selected from:
• 36%≦indium≦63%;
• 28%≦tin≦48%;
• and 2%≦bismuth 26%;
• 42%≦bismuth≦62%;
• 19%≦tin≦42%;
• and 7%≦indium 28%;
• 33%≦indium≦67%;
• 32%≦bismuth≦67%;
• and 0.1%≦tin≦20%;
• 52%≦indium≦54% indium;
• 0.01%≦zinc≦2%;
• and 46%≦tin≦48%;
• or
• 33%≦indium≦67%;
• 32%≦bismuth≦67%;
• and 0.1%≦zinc≦1%;
• and
• the solution, mixture, and reaction products of the solder;
• and
• a stress-compensation collar (SCC) disposed on a board, wherein the SCC partially embeds the solder first bump.

A computing system comprising:

• a board including a bottom and a land side;
• a substrate including a lower surface and an upper surface, wherein the board is disposed on the substrate land side;
• a solder first bump disposed on the lower surface, wherein the solder first bump is selected from:
• 36%≦indium≦63%;
• 28%≦tin≦48%;
• and 2%≦bismuth 26%;
• 42%≦bismuth≦62%;
• 19%≦tin≦42%;
• and 7%≦indium 28%;
• 33%≦indium≦67%;
• 32%≦bismuth≦67%;
• and 0.1%≦tin≦20%;
• 52%≦indium≦54% indium;
• 0.01%≦zinc≦2%;
• and 46%≦tin≦48%;
• or
• 33%≦indium≦67%;
• 32%≦bismuth≦67%;
• and 0.1%≦zinc≦1%;
• and
• the solution, mixture, and reaction products of the solder;
• and
• a stress-compensation collar (SCC) disposed on the board, wherein the solder first bump is at least partially embedded in the SCC;
• a die disposed upon the upper surface, wherein the die is coupled to the solder first bump;
• and
• at least one of an input device and an output device coupled to the solder first bump.