System and method for stress free conductor removal
AssigneeLam Research Corporation
InventorsAndrew Bailey, Shrikant Lohokare
Life of this patent
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Abstract
A system and method for forming a planar dielectric layer includes identifying a non-planarity in the dielectric layer, forming one or more additional dielectric layers over the dielectric layer and planarizing at least one of the additional dielectric layers wherein the one or more additional dielectric layers include at least one of a spin-on-glass layer and at least one of a low-k dielectric material layer and wherein each one of the one or more additional dielectric layers having a thickness of less than about 1000 angstroms and wherein the one or more additional dielectric layers has a total thickness of between about 1000 and about 4000 angstroms.
Claims16
A method for forming a semiconductor in a dual damascene structure comprising:
- receiving a patterned semiconductor substrate, having a first conductive interconnect material filling a plurality of features in the pattern, the first conductive interconnect material having an overburden portion;
- planarizing the overburden portion without imparting stress to the plurality of features;
- forming a subsequent dielectric layer on the planarized overburden portion;
- planarizing the subsequent dielectric layer including:
- identifying a non-planarity in the subsequent dielectric layer;
- forming one or more additional dielectric layers over the subsequent dielectric layer;
- and
- planarizing at least one of the additional dielectric layers;
- forming a mask on the planar subsequent dielectric layer;
- forming one or more features in the planar subsequent dielectric layer;
- and
- filling the one or more features with a second conductive interconnect material.
A method for forming a semiconductor in a dual damascene structure comprising:
- receiving a patterned semiconductor substrate, having a first conductive interconnect material filling a plurality of features in the pattern, the first conductive interconnect material having an overburden portion;
- planarizing the overburden portion without imparting stress to the plurality of features, a remaining planar overburden portion having a thickness of between about zero and about 500 angstroms;
- forming a subsequent dielectric layers on the planarized overburden portion;
- planarizing the subsequent dielectric layer including:
- identifying a non-planarity in the subsequent dielectric layer;
- forming at least one additional dielectric layer over the subsequent dielectric layer, each one of the one or more additional dielectric layers having a thickness of less than about 1000 angstroms and wherein the one or more additional dielectric layers has a total thickness of between about 1000 and about 4000 angstroms;
- and
- planarizing at least one of the additional dielectric layers;
- forming a mask on the planar subsequent dielectric layer;
- forming one or more features in the planar subsequent dielectric layer;
- and
- filling the one or more features with a second conductive interconnect material.
A method of forming a planar dielectric layer comprising:
- identifying a non-planarity in the dielectric layer;
- forming one or more additional dielectric layers over the dielectric layer;
- and
- planarizing at least one of the additional dielectric layers wherein the one or more additional dielectric layers include at least one of a spin-on-glass layer and at least one of a low-k dielectric material layer and wherein each one of the one or more additional dielectric layers having a thickness of less than about 1000 angstroms and wherein the one or more additional dielectric layers has a total thickness of between about 1000 and about 4000 angstroms.
Dependencies are inferred from the claim text.