Back to results
US 2007/0190740 A1Published application
Enhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistors
AssigneeInternational Business Machines Corporation
InventorsToshiharu Furukawa, Carl Radens, William Tonti, Richard Williams
Life of this patent
Estimating the term…
Abstract
Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
Claims12
1-21. (canceled)
An enhanced silicon-on-insulator (SOI) transistor comprising:
- a thin buried oxide (BOX) layer;
- an active channel region over said thin buried oxide (BOX) layer;
- a gate dielectric and a gate electrode over said active channel region;
- source/drain regions adjacent said active channel region;
- said source/drain regions having selective strain for enhanced carrier mobility for both P-channel and N-channel devices;
- and
- a thick self-aligned buried oxide (BOX) region under said source/drain regions.
4 more elements
Dependencies are inferred from the claim text.