Semiconductor device and method of manufacturing the same
AssigneeHynix Semiconductor Inc.
InventorWan Shin
Life of this patent
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Abstract
A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.
Claims14
A semiconductor device, comprising:
- a first well region formed in a semiconductor substrate;
- a second well region formed in the first well region and divide form the first well region;
- and
- a third well region formed in the first well region and being adjacent to a surface of the semiconductor substrate on the second well region.
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first well region in a semiconductor substrate;
- forming a trench in the semiconductor substrate of the first well region;
- filling the trench with a polysilicon layer;
- forming an impurity region connected to a bottom of the polysilicon layer in the first well region, thus forming a second well region to divide the first well region;
- and
- forming a third well region formed in the first well region and being adjacent to a surface of the semiconductor substrate on the second well region.
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first well region in a semiconductor substrate;
- forming a second well region formed in the first well region and divide from the first well region;
- and
- forming a third well region formed in the first well region and being adjacent to a surface of the semiconductor substrate on the second well region.
Dependencies are inferred from the claim text.