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US 2007/0190736 A1Published application
Overlay alignment mark and alignment method for the fabrication of trench-capacitor dram devices
AssigneeNanya Technology Corporation
InventorsAn-Hsiung Liu, Chiang-Lin Shih, Wen-Bin Wu, Hui-Min Mao, Lin-Chin Su, Pei-Ing Lee
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Abstract
A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.
Claims13
A method for fabricating a microelectronic device, comprising:
- providing a semiconductor substrate comprising thereon a device region and an alignment-mark forming region;
- forming a trench in the semiconductor substrate within the device region, and simultaneously, forming a previous-layer alignment pattern in the semiconductor substrate within the alignment-mark forming region, wherein the previous-layer alignment pattern comprises a plurality of trench lines;
- forming a capacitor structure within the trench comprising at least a conductive layer in the trench, wherein the trench lines also comprises the conductive layer;
- forming a first photo resist layer over the semiconductor substrate and performing an exposure process to form an opening in the first photo resist layer, wherein the opening only exposes the previous-layer alignment pattern in the alignment-mark forming region;
- using the first photo resist layer as a mask, performing an removing process to remove the conductive layer inside the trench lines;
- removing the first photo resist layer;
- forming a second photo resist layer over the semiconductor substrate;
- and
- patterning the second photo resist layer, and simultaneously, forming an existing-layer photo resist pattern within the alignment-mark forming region, wherein the existing-layer photo resist pattern and the previous-layer alignment pattern together form an overlay mark.
6 more elements
A method for fabricating a microelectronic device, comprising:
- providing a substrate comprising thereon a device region and an mark forming region;
- forming a trench in the substrate within the device region, and simultaneously, forming a first pattern structure in the substrate within the mark forming region, wherein the first pattern structure comprises a plurality of trench lines;
- forming at least a material in the trench and simultaneously forming the material in the trench lines;
- forming a first patterning layer over the substrate comprising an opening, wherein the opening exposes the first pattern structure in the mark forming region;
- removing at least a part of the material inside the trench lines;
- and
- removing the first patterning layer
4 more elements
Dependencies are inferred from the claim text.