Resolving pattern-loading issues of SiGe stressor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Lien Huang, Jim Huang, Ling-Yen Yeh, Hun-Jan Tao
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Abstract
A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielectric, forming a recess in the semiconductor adjacent the spacer, and depositing SiGe in the recess to form a SiGe stressor. The method further includes etching the SiGe stressor to improve the uniformity of SiGe stressors.
Claims23
A method for forming a semiconductor structure, the method comprising:
- providing a semiconductor substrate;
- forming a gate dielectric over the semiconductor substrate;
- forming a gate electrode on the gate dielectric;
- forming a spacer on a sidewall of the gate electrode and the gate dielectric;
- forming a recess in the semiconductor substrate substantially aligned with an edge of the spacer;
- depositing SiGe in the recess to form a SiGe stressor;
- and
- etching the SiGe stressor to reduce a thickness of the SiGe stressor.
A method for forming a semiconductor structure, the method comprising:
- providing a semiconductor substrate including a dense region and an iso region;
- forming a first gate dielectric in the dense region and a second gate dielectric in the iso region;
- forming a first gate electrode on the first gate dielectric and a second gate electrode on the second gate dielectric;
- forming a first spacer on a sidewall of the first gate electrode and the first gate dielectric and a second spacer on a sidewall of the second gate electrode and the second gate dielectric;
- forming a first recess in the semiconductor substrate substantially aligned with an edge of the first spacer and a second recess in the semiconductor substrate substantially aligned with an edge of the second spacer;
- epitaxially growing a first SiGe stressor in the first recess and a second SiGe stressor in the second recess, the second SiGe stressor having a greater growth rate than the first stressor;
- and
- etching the first and the second stressors to substantially reduce a difference in thickness between the first and the second SiGe stressors, wherein the second SiGe stressor has a substantially greater etching rate than the first SiGe stressor.
A method for forming a semiconductor structure, the method comprising:
- providing a semiconductor substrate;
- and
- forming a SiGe stressor in a source/drain region of a PMOS device comprising:
- forming a recess in the source/drain region;
- and
- performing at least one cycle, wherein each cycle comprises:
- depositing SiGe in the recess to increase a thickness of the SiGe stressor;
- and
- etching the SiGe stressor to reduce the thickness.
Dependencies are inferred from the claim text.