Method to form upward pointing p-i-n diodes having large and uniform current
AssigneeSanDisk 3D LLC
InventorS. Herner
Life of this patent
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Abstract
A method is disclosed to form an upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array.
Claims21
A method for forming a vertically oriented p-i-n diode, the method comprising:
- forming a first rail-shaped conductor above a substrate;
- forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductor;
- forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type region of semiconductor material, wherein the deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy;
- patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a pillar;
- forming a top heavily doped n-type region doped with arsenic;
- and
- annealing to crystallize the semiconductor material, where some portion of the semiconductor material was amorphous as deposited and is in contact with a silicide, germanide, or silicide-germanide after the annealing step,
- wherein the p-i-n diode comprises the bottom heavily doped p-type region, the middle intrinsic or lightly doped region, and the top heavily doped n-type region.
A method for forming a monolithic three dimensional memory array, the method comprising:
- a) monolithically forming a first memory level above a substrate by:
- i) forming a first plurality of rail-shaped conductors above the substrate;
- ii) forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductors;
- iii) forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type semiconductor, wherein the deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy;
- iv) patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a first plurality of pillars;
- v) forming a top heavily doped region doped with arsenic;
- vi) annealing to crystallize the semiconductor material, where some portion of the semiconductor material was amorphous as deposited and is in contact with a silicide, germanide, or silicide-germanide after the annealing step;
- and
- vii) forming a second plurality of rail-shaped conductors above the middle intrinsic or lightly doped region, wherein the first memory level comprises a first plurality of memory cells, each first memory cell comprising a portion of one of the first rail-shaped conductors, one of a first plurality of pillars, and a portion of one of the second conductors,
- wherein each of the first pillars comprises a p-i-n diode comprising a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region formed by the doping step, and
- b) monolithically forming a second memory level above the first memory level.
Dependencies are inferred from the claim text.