Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same
AssigneeSamsung Electronics Co., Ltd.
InventorJi-Young Kim
Life of this patent
Estimating the term…
Abstract
Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation region and the sidewall of the gate trench, is etched to expose the remaining substrate region. Thereafter, the exposed portion of the remaining substrate region is removed to form a substantially flat bottom of the gate trench. The recess transistor manufactured by the provided method has the same channel length regardless of the locations of the recess transistor in an active region.
Claims4
A method of fabricating a recess transistor, the method comprising:
- forming a trench device isolation region on an integrated circuit substrate to define an active region;
- forming a gate trench in the active region;
- etching the trench device isolation region, which contacts the sidewall of the gate trench, and a substrate region remaining between the sidewall of the trench device isolation region and the sidewall of the gate trench, to expose the remaining substrate region;
- removing the exposed portion of the remaining substrate region to form a substantially flat bottom of the gate trench;
- and
- forming a recess gate that fills the gate trench.
A recess transistor in an integrated circuit device, the recess transistor comprising:
- a source/drain region formed in an active region of an integrated circuit substrate;
- and
- a recess gate formed in the integrated circuit substrate, the recess gate having a depth greater than a junction depth of the source/drain region and having a substantially flat bottom.
A recess transistor comprising:
- a source/drain region formed in an active region that is defined by a shallow trench device isolation region in an integrated circuit substrate;
- a recess gate formed in the integrated circuit substrate that has a depth greater than a junction depth of the source/drain region;
- and
- a channel, a length of the channel at the edge of the active region substantially the same as a length of the channel at the center of the active region.
Dependencies are inferred from the claim text.